GAA Semiconductor Devices With CPODE Gate Height Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes to improve integration density, challenges arise in manufacturing gate-all-around (GAA) semiconductor devices, particularly in forming shallow CPODE (Continuous Poly On Diffusion Edge) structures without damaging source/drain regions and maintaining accurate gate height control.
Innovation Solution
The solution involves forming a multi-layer structure with nanosheets over a semiconductor substrate, creating fins and gate electrodes, and using a Continuous Poly On Diffusion Edge (CPODE) structure to divide fins and intersect cut-metal gate structures. This process includes forming inner and bottom spacers, source/drain regions, and a dielectric structure through the gate electrode and into the substrate, ensuring isolation of source/drain regions from the substrate and precise control of gate height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but manufacturing challenges arise that damage source/drain regions and compromise device integrity
Solution Approach 1:
The patent segments the gate structure into multiple components including gate electrodes, gate dielectric, and CPODE structures that divide the fin regions. This segmentation allows for precise control of each component during fabrication, enabling reduced feature sizes while maintaining manufacturing precision and protecting source/drain regions from damage
Solution Approach 2:
The patent employs preliminary actions by forming isolation regions and CPODE structures before completing the gate electrode formation. These preliminary structures protect the source/drain regions during subsequent processing steps, preventing damage while enabling continued scaling of feature sizes
2Manufacturing precision
If shallower CPODE structures are formed to maintain accurate gate height control, then gate height precision is improved, but the process becomes more complex and difficult to manufacture
Solution Approach 1:
The patent transitions from controlling gate height through single-dimensional etch depth control to a multi-dimensional approach using CPODE structures that extend horizontally along the fin. This dimensional change provides an additional degree of freedom for controlling effective gate height while simplifying the manufacturing process through self-aligned formation
3Reliability
If source/drain regions are isolated from the substrate to prevent damage, then device reliability is improved, but additional manufacturing steps are required increasing process complexity
Solution Approach 1:
The patent merges the isolation function with the CPODE structure formation process. The same dielectric material deposition and etching steps that create the CPODE structures also form the isolation regions, combining multiple functions into a unified process sequence that reduces overall process complexity while maintaining source/drain protection
Data Source
AI summary
Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.