Gate-All-Around Semiconductor Device With Lateral Structures
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to challenges in achieving high integration density, particularly in manufacturing fine patterns and overcoming the limitations of planar metal oxide semiconductor FETs, necessitating the development of semiconductor devices with improved electrical properties and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, gate structures, channel layers, source/drain regions, and lateral structures, where the gate structures include dielectric layers and electrode layers stacked in order, and lateral structures are interposed between the second gate dielectric layer and electrode layer, enhancing electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar metal oxide semiconductor FET structure is used, then manufacturing is simpler, but electrical properties and performance are limited
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel width and surface area for carrier transport, significantly improving electrical properties such as drive current and transconductance while maintaining manufacturability through established semiconductor processing techniques.
Solution Approach 2:
The gate structure completely surrounds the channel region in a wrap-around configuration, with the gate electrode enveloping the fin structure from multiple sides. This nested gate-all-around configuration provides superior electrostatic control over the channel compared to planar gates, enhancing device performance and reliability without substantially complicating the manufacturing process.
2Productivity
If integration density is increased, then device performance improves, but pattern fabrication difficulty increases
Solution Approach 1:
By utilizing the vertical dimension with fins extending upward from the substrate, the patent achieves higher effective channel width within the same planar footprint. This allows increased integration density without requiring proportionally smaller lateral feature sizes, thereby avoiding the exponential increase in fabrication difficulty that would result from further planar scaling.
Data Source
AI summary
A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure extending in a second direction intersecting the active region on the substrate and including a gate dielectric layer and a gate electrode, channel layers spaced apart from each other in a third direction perpendicular to an upper surface of the substrate on the active region and surrounded by the gate structure, a lateral structure disposed on internal side surfaces of the gate dielectric layer and contacting the gate dielectric layer and the gate electrode, and source/drain regions disposed in regions in which the active region is recessed on opposite sides of the gate structure, and connected to the channel layers. A level of lower surfaces of the lateral structures is higher than a level of a lower surface of the gate electrode.