GAA Semiconductor Structure With Insulated N-Type Stack

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Solution Overview

Problem

Semiconductor devices with a Gate All Around (GAA) structure have complex manufacturing processes, leading to increased costs due to the higher number of processes involved.

Innovation Solution

A semiconductor device with a low-concentration N-type region, two high-concentration N-type regions, a gate electrode, and insulating films is designed, where the high-concentration regions are connected to the source and drain electrodes, and the gate electrode surrounds the low-concentration N-type region, simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a Gate All Around (GAA) structure is used to surround the channel with a gate electrode, then the transistor performance is improved by preventing interface traps from affecting the channel, but the manufacturing process becomes complicated and costs increase due to the higher number of processes involved

Engineering Contradiction:
Improvetransistor performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from a planar gate structure to a three-dimensional Gate All Around structure where the gate electrode completely surrounds the channel in the vertical stacking direction. This dimensional change allows the gate to control the channel from all directions, improving transistor performance by isolating the channel from interface traps at the semiconductor-substrate interface, while the insulating films manage the complexity of this 3D configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces insulating films as intermediary elements between the gate electrode and the semiconductor regions. These insulating films serve as mediators that electrically isolate the gate from the high-concentration N-type regions while allowing the gate to maintain electrostatic control over the low-concentration N-type channel, thus resolving the conflict between achieving full surround control and preventing unwanted electrical interactions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If a Gate All Around structure is used to surround the channel with a gate electrode, then the channel is protected from interface traps, but the number of manufacturing processes increases leading to higher costs

Engineering Contradiction:
Improveinterface trap effectsVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent applies local quality by creating distinct impurity concentration zones within the semiconductor structure. The low-concentration N-type region forms the channel with reduced interface trap effects, while the high-concentration N-type regions provide electrical connection points. This localized differentiation of impurity concentrations allows the channel to be protected from interface traps specifically where needed, without requiring complex manufacturing processes throughout the entire device structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements a nested structure where the low-concentration N-type channel region is surrounded by the gate electrode, which is in turn isolated by insulating films from the high-concentration N-type regions. This nested arrangement of regions with different impurity concentrations, surrounded by gating structures and insulating layers, protects the channel from interface traps while maintaining a manageable manufacturing process through systematic layering.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12243884B2Semiconductor device and solid-state imaging sensor
Publication Date: 2025.03.04 SONY SEMICON SOLUTIONS CORP
  • US12243884B2 patent drawing
  • US12243884B2 patent drawing
  • US12243884B2 patent drawing

AI summary

A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.