Gate-All-Around Semiconductor Device With Segmented Nanosheet Gates
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Solution Overview
Problem
Current semiconductor devices with gate-all-around structures face challenges in scaling down while effectively controlling current and suppressing short channel effects without increasing gate length.
Innovation Solution
The semiconductor device incorporates a unique layout with multiple fin-type patterns and gate patterns intersecting each other, along with nanosheet structures and insulating films, to enhance current control and reduce short channel effects, including specific configurations in SRAM regions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate-all-around structure is used to scale down devices, then device size is reduced and current control capability is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is divided into multiple discrete gate electrodes (first gate electrode, second gate electrode, third gate electrode, fourth gate electrode) that wrap around the channel from different directions. This segmentation allows the complex 3D gate-all-around structure to be constructed through systematic fabrication steps, making the complex structure manufacturable while maintaining superior current control.
2Reliability
If gate length is increased to suppress short channel effects, then current control improves, but device area increases
Solution Approach 1:
The gate structure transitions from a conventional planar 2D gate to a three-dimensional gate-all-around structure where gates wrap around the channel from multiple directions (top, bottom, and sides). This dimensional change provides enhanced electrostatic control over the channel without increasing the horizontal gate length, thereby suppressing short channel effects while maintaining compact device footprint.
3Reliability
If multiple gate patterns are added to improve current control, then current control capability increases, but device complexity increases
Solution Approach 1:
Multiple gate electrodes are merged into a unified gate-all-around structure that collectively controls the channel. The first, second, third, and fourth gate electrodes are positioned to wrap around the channel from different directions, creating a coordinated system where all gates work together to control carrier flow, thereby enhancing current control capability while managing complexity through functional integration.
Data Source
AI summary
A semiconductor device includes first and second fin type patterns, first and second gate patterns intersecting the first and second fin type patterns, third and fourth gate patterns intersecting the first fin type pattern between the first and the second gate patterns, a fifth gate pattern intersecting the second fin type pattern, a sixth gate pattern intersecting the second fin type pattern, first to third semiconductor patterns disposed among the first, the third, the fourth and the second gate patterns, and fourth to sixth semiconductor patterns disposed among the first, the fifth, the sixth and the second gate patterns. The first semiconductor pattern to the fourth semiconductor pattern and the sixth semiconductor pattern are electrically connected to a wiring structure, and the fifth semiconductor pattern is not connected to the wiring structure.