Gate-All-Around Semiconductor Structure With Recessed Outer Spacers
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Solution Overview
Problem
Conventional fin field effect transistors have limitations in pinch-off of off-state current and increasing operating current due to restricted channel control and small channel volume, which is addressed by the introduction of a gate-all-around (GAA) structure, but further improvements are needed to enhance control and current capacity.
Innovation Solution
A semiconductor structure with vertically stacked channel layers, isolation grooves, inner and outer spacers, and gate structures that surround the channel layers, where the outer spacers are recessed to improve etching efficiency and increase contact areas between source/drain doped layers and channel layers, enhancing the isolation effect and operating current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fin field effect transistor structure is used, then manufacturing process is simple, but channel control is limited and off-state current pinch-off is insufficient
Solution Approach 1:
The patent transitions from a planar fin structure to a vertically stacked three-dimensional structure with multiple channel layers. The gate wraps around the channels in all directions (gate-all-around configuration), providing omnidirectional control of the channel current. This dimensional change enables effective pinch-off of off-state current while maintaining scalability for advanced technology nodes.
Solution Approach 2:
The gate structure is nested around the channel layers in a gate-all-around configuration, with the gate dielectric layer and gate electrode layer completely surrounding the channel regions. This nested arrangement provides maximum gate control over the channel current from all directions, significantly improving off-state current suppression compared to conventional three-sided gate structures.
2Power
If conventional fin field effect transistor structure is used, then device structure is simple, but channel volume is small and operating current cannot be increased
Solution Approach 1:
The patent employs vertically stacked channel layers extending in the third dimension (vertical direction) while maintaining lateral extension. This three-dimensional channel structure dramatically increases the total channel volume and effective channel area compared to conventional two-dimensional fin structures, enabling higher operating currents while maintaining scalability.
Solution Approach 2:
The channel region is segmented into multiple discrete channel layers stacked vertically, with isolation grooves between adjacent channels. This segmentation allows each channel layer to contribute independently to the total current while maintaining excellent gate control. The isolated channels can be individually optimized and provide cumulative current capacity.
3Ease of manufacture
If outer spacers are not recessed, then fabrication process is simple, but etching difficulty is high and isolation groove morphology is poor
Solution Approach 1:
The outer spacers are recessed relative to the channel layer end surfaces before forming the isolation grooves. This preliminary action creates optimized etching access and exposes the channel ends, enabling better etching control and forming isolation grooves with superior morphology. The recessed spacers serve as preliminary structures that facilitate subsequent processing steps.
4Power
If source/drain doped layers are formed without recessed outer spacers, then process steps are fewer, but contact area between source/drain and channel is limited
Solution Approach 1:
The outer spacers are recessed before forming the source and drain doped layers, creating enlarged contact areas between the source/drain regions and the channel layers. This preliminary recess action exposes more channel surface area, allowing the subsequently formed source/drain doped layers to establish larger contact interfaces, thereby increasing current capacity.
Data Source
AI summary
A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate; channel layers on the substrate vertically stacked along a normal direction of a surface of the substrate and extend along a first direction parallel to the surface of the substrate; an isolation layer over the substrate; isolation grooves between ends of adjacent channel layers; inner spacers in the isolation grooves vertically isolating channel layers; gate structures over the isolation layer surrounding a portion of channel layers along a second direction perpendicular to the first direction; outsider spacers at sidewalls of the gate structures; source/drain doped layers at two sides of each gate structure; and a dielectric layer over the isolation layer covering a portion of the channel layers and the gate structures and exposes top surfaces of the gate structures.