GAA Semiconductor Structure with SiGe Passivation for Carrier Mobility
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to the complexity of fabricating the GAA features around nanowires, necessitating improvements in the semiconductor manufacturing process to enhance gate control and reduce short-channel effects.
Innovation Solution
A semiconductor structure is formed with passivation layers on exposed etched surfaces of SiGe layers using radicals such as nitrogen, hydrogen, or sulfur to bond with dangling bonds, reducing interface trap density and improving carrier mobility, and a method involving multiple passivation processes to mitigate oxide formation and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices (GAA) are introduced to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming sacrificial nanowire structures, depositing gate materials, removing sacrificial material, and forming final GAA structures. This segmentation allows complex GAA fabrication to be broken down into manageable steps that can be integrated into existing CMOS processes.
Solution Approach 2:
The patent uses sacrificial nanowire structures as intermediary elements during fabrication. These temporary structures serve as placeholders that guide gate material deposition and are later removed to create the final GAA configuration, simplifying the overall fabrication complexity.
2Adaptability or versatility
If conventional processes are used for GAA fabrication, then compatibility with CMOS is maintained, but integration challenges persist
Solution Approach 1:
The patent employs universal materials and processes that function across multiple device types. The sacrificial nanowire structures and gate materials can be used for both n-type and p-type GAA devices, maintaining CMOS compatibility while simplifying integration through standardized fabrication steps.
3Reliability
If passivation layers are formed to reduce interface trap density, then carrier mobility is improved, but process steps increase
Solution Approach 1:
The patent applies passivation layers to exposed etched surfaces of SiGe layers before subsequent processing steps. This preliminary passivation reduces interface trap density and improves carrier mobility early in the process, preventing degradation in later thermal processes rather than requiring corrective steps afterward.
Solution Approach 2:
The patent uses radical-based passivation (nitrogen, hydrogen, or sulfur radicals) to chemically modify the surface properties of SiGe layers. This parameter change in surface chemistry reduces interface trap density and improves carrier mobility without requiring additional structural layers that would increase process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation of dangling bonds and subsequent thermal processes improve the performance of semiconductor devices by reducing interface trap density and enhancing carrier mobility, thereby improving the efficiency and reliability of GAA devices.
Implementation Method 1
passivation layers on exposed etched surfaces of SiGe layers using radicals such as nitrogen, hydrogen, or sulfur to bond with dangling bonds
Implementation Method 2
The passivation of dangling bonds and subsequent thermal processes improve the performance of semiconductor devices
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, an inner spacer layer sandwiched between the source/drain feature and the gate stack and between the first nanostructure and the second nanostructure, a semiconductor feature at a corner between the inner spacer layer and the first nanostructure, and a first passivation layer sandwiched between a first surface of the semiconductor feature and the gate stack.