GAA Silicon and SiGe Channels With a Common Gate Metal
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Solution Overview
Problem
The use of multiple gate electrodes in multi-gate MOSFETs requires additional processing steps due to different optimal work functions for p-type and n-type field effect transistors, increasing manufacturing costs and time.
Innovation Solution
Employing a common gate metal for both p-type and n-type field effect transistors by utilizing silicon as the semiconductor channel material for n-type transistors and a silicon-germanium alloy for p-type transistors, allowing for shared gate electrode materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different gate electrode materials are used for p-type and n-type field effect transistors to optimize work functions, then device performance is improved, but manufacturing complexity and processing steps increase
Solution Approach 1:
The patent merges the gate electrode structures of p-type and n-type field effect transistors by forming a common gate electrode that extends over both types of transistors. This is achieved by depositing gate electrode material (such as tungsten, titanium nitride, or tantalum nitride) in a single continuous process that covers both p-type and n-type device regions, thereby eliminating the need for separate gate electrode formation steps while maintaining optimized work functions for both transistor types.
Solution Approach 2:
The common gate electrode material serves multiple functions simultaneously: it acts as the gate electrode for both p-type and n-type field effect transistors, provides work function optimization for both device types, and enables a unified manufacturing process. The gate electrode material is selected and deposited to provide appropriate electrical characteristics for controlling both n-type and p-type channels, making it a universal component for heterogeneous transistor integration.
2Reliability
If separate gate electrode formation processes are used for p-type and n-type transistors, then optimal work functions are achieved, but manufacturing time and costs increase
Solution Approach 1:
The patent combines multiple gate electrode formation operations into a single integrated process step. By depositing gate electrode material in one continuous deposition sequence that covers both p-type and n-type transistor regions, the manufacturing process eliminates redundant steps such as separate material deposition, patterning, and etching operations that would otherwise be required for each transistor type, thereby significantly improving manufacturing throughput.
Solution Approach 2:
The patent performs preliminary actions by pre-defining the gate electrode material composition and deposition parameters before the actual deposition process. The gate electrode material is selected and prepared in advance to have appropriate properties for both p-type and n-type transistors, and the deposition process is configured to simultaneously form optimized gate electrodes for both device types in a single operation, eliminating the need for subsequent adjustments or reprocessing.
3Reliability
If multiple gate electrodes with different materials are used, then device performance is optimized, but additional processing steps and materials are required
Solution Approach 1:
The patent merges the formation of gate electrodes for p-type and n-type field effect transistors into a single manufacturing operation. A common gate electrode material is deposited in one continuous process step that covers both device regions, eliminating the need for separate material deposition, patterning, and etching steps that would otherwise be required for each transistor type, thereby simplifying the manufacturing process while maintaining device performance.
Solution Approach 2:
The common gate electrode material is selected to serve multiple functions: it provides the gate electrode function for both p-type and n-type transistors, delivers optimized work function characteristics for both device types, and enables a simplified unified manufacturing process. This universal material approach eliminates the complexity of handling multiple different gate electrode materials and their associated separate processing steps.
Data Source
AI summary
A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.