GAA Transistor Isolating Feature Under Source/Drain Leakage Paths

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Solution Overview

Problem

Integration of gate-all-around (GAA) transistors in semiconductor manufacturing is challenging due to issues with source/drain structures causing off-state leakage current paths when connected directly to the substrate, which complicates the manufacturing process and affects device performance.

Innovation Solution

Incorporation of an isolating feature between the source/drain structures and the substrate to prevent direct electrical contact, using methods like epitaxial growth and etching processes to form isolating features made of undoped semiconductor materials or insulating materials, which separate the source/drain structures from the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If source/drain structures are directly connected to the substrate, then manufacturing process is simpler, but off-state leakage current increases

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidoff-state leakage current
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An isolating feature (such as a dielectric layer or undoped semiconductor region) is introduced between the source/drain structures and the substrate. This intermediary element blocks the direct electrical contact that causes leakage current, while adding minimal complexity to the manufacturing process. The isolating feature acts as a mediator that prevents harmful current paths without requiring complete redesign of the device architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If isolating feature is added to separate source/drain from substrate, then off-state leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveoff-state leakage currentVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device structure is segmented by dividing the region between source/drain and substrate into distinct functional zones. The isolating feature creates a clear separation between the active device region and the substrate, allowing each segment to be optimized independently. This segmentation approach manages complexity by organizing the structure into manageable, functionally distinct sections rather than treating it as a monolithic complex system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The isolating feature is applied locally only where needed - specifically in the regions where source/drain structures contact or approach the substrate. Rather than uniformly complicating the entire device structure, the isolation is implemented only at the critical leakage points, maintaining simplicity in non-critical areas while addressing the specific reliability issue where it occurs.

Inventive Principle:
Principle #3Local quality

3Reliability

If gate-all-around structure is implemented, then gate control is improved, but integration challenges increase

Engineering Contradiction:
Improvegate controlVSAvoidintegration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolating features are formed in advance during the fabrication sequence, before the gate-all-around structures are fully assembled. By preparing the isolation regions early in the process, the subsequent integration of the complex gate structure is simplified, as the leakage prevention mechanism is already in place to guide and constrain the gate formation steps.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Reduces off-state leakage current and enhances the performance of GAA transistors by minimizing current leakage paths, thereby improving the overall efficiency and reliability of the semiconductor structure.

Implementation Method 1

Incorporation of an isolating feature between the source/drain structures and the substrate to prevent direct electrical contact

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

using methods like epitaxial growth and etching processes to form isolating features

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12471353B2Gate-all around transistor with isolating feature under source/drain
Publication Date: 2025.11.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12471353B2 patent drawing
  • US12471353B2 patent drawing
  • US12471353B2 patent drawing

AI summary

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes semiconductor material layers stacked above a substrate along a first direction and a gate structure wrapping around the semiconductor material layers. The semiconductor structure further includes an epitaxial structure coupled to the semiconductor material layers in a second direction that is different from the first direction and a SiGe-containing layer located below the epitaxial structure. In addition, a material of the SiGe-containing layer is different from a material of the epitaxial structure, the SiGe-containing layer comprises a first portion with a first thickness in the first direction, and a second portion with a second thickness in the first direction, and the second thickness is smaller than the first thickness.