Gate-All-Around SONOS Memory Cell for Scaled 3D Operation Control
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Solution Overview
Problem
The integration of non-volatile memory in semiconductor devices faces challenges in scaling down to smaller sizes while maintaining performance and functionality, particularly in three-dimensional designs, where existing technologies struggle to efficiently control memory operations and reduce device size effectively.
Innovation Solution
The implementation of a 1.5-transistor (1.5T) SONOS non-volatile memory cell with a gate-all-around structure, comprising a semiconductor wire with a gate dielectric layer and stacked dielectric layers, allows for precise control of memory operations and reduces device size by employing a select transistor and a control transistor with a gate-all-around configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional floating gate designs are used, then device functionality is maintained, but device size cannot be effectively reduced
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first control gate, second control gate, select gate) that wrap around the semiconductor wire from different directions. This segmentation allows each gate to independently control specific memory operations, achieving precise control while minimizing the overall device footprint through three-dimensional spatial arrangement.
Solution Approach 2:
The patent transitions from planar two-dimensional gate control to three-dimensional gate-all-around control. The gates are arranged in multiple dimensions around the semiconductor wire, enabling comprehensive control of memory operations from all directions. This dimensional change increases control precision while reducing the lateral footprint of the device.
2Quantity of substance
If device density is increased through scaling, then higher device density is achieved, but control precision over memory operations deteriorates
Solution Approach 1:
Memory operations are divided into distinct control functions handled by separate gates. The first control gate controls write operations, the second control gate controls erase operations, and the select gate controls read operations. This functional segmentation maintains control precision even as device dimensions are reduced, because each gate is optimized for its specific operation rather than sharing a single control mechanism.
Solution Approach 2:
Different regions of the gate structure are assigned different functional qualities. The gates are positioned at specific locations around the semiconductor wire to optimize control over charge trapping and release in different regions. This local functional differentiation ensures precise control over memory operations while allowing compact device scaling.
3Adaptability or versatility
If three-dimensional designs are implemented, then functionality is enhanced, but control complexity increases
Solution Approach 1:
The complex three-dimensional control functionality is segmented into discrete, independently controllable gates. Each gate handles a specific aspect of memory operation (write, erase, read), simplifying the control logic despite the three-dimensional architecture. This segmentation allows the complex functionality to be managed through modular, independent control mechanisms rather than a single complex control system.
Data Source
AI summary
A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.