Gate-All-Around Nanowire Layout With Source/Drain Substrate Contact
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining short channel control and mobility, particularly due to constraints on lithographic processes, and there is a lack of effective solutions for nanowire and nanoribbon architectures to dissipate charge during in-process charging and electrostatic discharge events.
Innovation Solution
The implementation of a patterned epitaxial source or drain undercut process to create a connection between nanowire/nanoribbon structures and a silicon substrate, allowing for charge dissipation through an extended epitaxial undercut process, which includes forming additional regions for substrate contact and using epitaxial growth to contact the nanowire/nanoribbon stack with the substrate, thereby providing a path for charge dissipation during in-process charging and electrostatic discharge events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanowire/nanoribbon structures are fabricated without substrate contact, then device density and scaling are improved, but charge dissipation capability deteriorates
Solution Approach 1:
The patent applies local quality by creating selective substrate contact regions through patterned epitaxial undercut processes. Only specific areas of the nanowire/nanoribbon structure establish electrical contact with the substrate, while other regions maintain isolation. This localized approach enables charge dissipation at contact points while preserving high device density and scaling benefits in non-contact regions.
Solution Approach 2:
The patent introduces a vertical dimension for substrate contact by forming deep trenches that extend beneath the nanowire/nanoribbon structure. This vertical pathway allows charge dissipation to occur in the depth dimension rather than requiring lateral spacing, enabling effective charge management without compromising planar device density.
2Productivity
If lithographic feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent employs preliminary action by forming the patterned epitaxial undercut structure and substrate contact regions before final nanowire/nanoribbon fabrication. This pre-established contact infrastructure remains valid through subsequent scaling steps, allowing lithographic features to be reduced without requiring re-patterning of charge dissipation pathways, thereby maintaining manufacturing precision during scaling.
Solution Approach 2:
The patent introduces an intermediary epitaxial layer structure that mediates between the lithographically defined pattern and the underlying substrate. This intermediate layer can be selectively removed or modified to create contact regions, decoupling the lithographic precision requirements from the final contact formation and enabling easier scaling.
3Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then ease of manufacture is improved, but short channel control deteriorates
Solution Approach 1:
The patent segments the substrate interaction by creating discrete, localized contact regions rather than continuous bulk silicon contact. The patterned epitaxial undercut process divides the substrate interface into distinct contact and non-contact zones, allowing simplified bulk silicon processing while achieving the short channel control benefits typically associated with more complex substrate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures proper protection of transistors during in-process charging and electrostatic discharge events, ensuring circuit functionality and improving the robustness of nanowire and nanoribbon transistor architectures by enabling effective charge dissipation.
Implementation Method 1
using epitaxial growth to contact the nanowire/nanoribbon stack with the substrate
Data Source
AI summary
Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.