GAA Source/Drain Epitaxy for Void-Free Core Layer Growth
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Solution Overview
Problem
As semiconductor devices shrink in size, they face issues such as short channel effects, increased source/drain electron tunneling, and performance degradation due to poor growth of epitaxial layers in nanostructure transistors like GAA devices, leading to voids, defects, parasitic resistance, and contact resistance.
Innovation Solution
A deposition recipe with a lower temperature and higher pressure is used to form a core epitaxial layer in the source/drain region of GAA devices, promoting uniform growth and reducing the likelihood of defects, while adjusting the germanium content in the core and capping epitaxial layers to minimize parasitic and contact resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition recipes are used to form epitaxial layers in source/drain regions, then the deposition process is simple and fast, but the epitaxial layers exhibit poor growth with voids, defects, high parasitic resistance, and high contact resistance
Solution Approach 1:
The patent applies parameter changes by modifying deposition temperature and pressure parameters. Specifically, it uses a first deposition temperature in a first range and a second deposition temperature in a second range (different from the first), along with corresponding pressure adjustments. These parameter changes enable uniform epitaxial layer growth without voids or defects while maintaining process control
Solution Approach 2:
The patent implements preliminary action by forming a buffer region before forming the main epitaxial layer. The buffer region is deposited first with specific temperature and pressure parameters, then subsequent epitaxial layers are formed on top. This preliminary deposition step prepares the surface and prevents defects in the final structure
2Length of moving object
If the gate length is reduced for smaller technology nodes, then the transistor size decreases, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The patent applies beforehand cushioning by forming a buffer region at the source/drain interface before the main channel region. This buffer region with specific material composition and structure cushions against the harmful electron tunneling effect, reducing off-state current while allowing scaled gate lengths for advanced technology nodes
3Reliability
If germanium content is increased in epitaxial layers, then carrier mobility improves, but parasitic resistance and contact resistance increase
Solution Approach 1:
The patent applies local quality by creating regions with different germanium contents at different locations. The buffer region has a specific germanium content optimized for interface quality and low resistance, while subsequent epitaxial layers have different germanium contents optimized for carrier mobility in the channel. This spatial variation in composition optimizes both mobility and resistance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of GAA devices by reducing voids and defects, lowering parasitic and contact resistances, thereby improving the overall yield and efficiency of the semiconductor device.
Implementation Method 1
forming a first epitaxial layer at a bottom of the recess; forming a second epitaxial layer on the first epitaxial layer
Data Source
AI summary
Some implementations described herein include a semiconductor device including a gate-all-around transistor. The gate-all-around transistor includes a source/drain region having a core epitaxial layer and a capping epitaxial layer. The core epitaxial layer is formed within the source/drain region using a deposition recipe having a temperature that is lesser relative to temperatures of other deposition recipes used to form other epitaxial layers, including the capping layer, within the source/drain region. The deposition recipe further includes a pressure that is greater relative to pressures of the other deposition recipes used to form the other epitaxial layers within the source/drain region. The temperature and pressure of the deposition recipe used to form the core epitaxial layer promote a uniform growth of the core epitaxial layer within the source/drain region. In this way, a likelihood of voids and/or defects is reduced to increase a yield of a semiconductor device including the core epitaxial layer.