GAA Source/Drain Isolation Structures for Leakage Suppression
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Solution Overview
Problem
Gate-all-around (GAA) field effect transistors (FETs) are susceptible to leakage currents due to parasitic channel formation between source/drain terminals and the semiconductor substrate, which degrades performance and increases power consumption, and existing solutions like substrate doping are costly or ineffective.
Innovation Solution
The implementation of isolation structures between the source/drain epitaxial layers and the semiconductor substrate, formed through an oxygen treatment like directional decoupled plasma oxidation (DDPO), to electrically isolate the source/drain epitaxial layers and eliminate the need for substrate doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate doping is used to prevent leakage currents, then leakage suppression is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
An isolation structure is introduced as an intermediary element between the source/drain epitaxial layers and the semiconductor substrate. This isolation structure acts as a mediator that prevents direct electrical contact, thereby suppressing leakage currents without requiring substrate doping. The isolation structure includes an insulating layer that physically and electrically separates the conductive source/drain regions from the substrate, eliminating the need for complex doping processes.
Solution Approach 2:
The structure is segmented by introducing a distinct isolation layer that divides the continuous electrical path between source/drain and substrate into separate regions. This segmentation creates an insulating barrier that breaks the leakage path, allowing the device to achieve low leakage current without the need for substrate modification through doping.
2Reliability
If counter-doping is applied to suppress parasitic channels, then leakage currents are reduced, but manufacturing cost increases
Solution Approach 1:
The isolation structure serves as a passive intermediary that eliminates the need for active counter-doping processes. By providing a physical insulating barrier, the isolation structure achieves leakage suppression through geometric and material separation rather than chemical modification of the substrate, thereby reducing manufacturing costs associated with doping facilities and process control.
Solution Approach 2:
The isolation structure uses a simple insulating layer that can be formed through standard deposition processes, replacing the need for expensive and complex counter-doping operations. The isolation structure achieves its function through its presence and material properties rather than requiring additional processing steps, making it a cost-effective solution.
3Device complexity
If source/drain epitaxial layers are grown directly on substrate, then device structure is simplified, but leakage paths form between source/drain and substrate
Solution Approach 1:
An isolation structure is positioned between the source/drain epitaxial layers and the semiconductor substrate to prevent direct contact. This intermediary layer maintains the simple epitaxial growth process while introducing a thin insulating barrier that blocks leakage paths without complicating the overall device architecture or growth procedure.
Solution Approach 2:
The isolation structure applies local quality modification by introducing insulating properties only in the specific region where source/drain contacts the substrate, rather than modifying the entire substrate or device structure. This localized approach prevents leakage at the critical interface while maintaining the simplicity of the overall epitaxial structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses leakage currents and reduces power consumption in GAA FETs by providing adequate electrical isolation, eliminating the requirement for counter-doping and enhancing the transistor's performance.
Implementation Method 1
formed through an oxygen treatment like directional decoupled plasma oxidation (DDPO)
Data Source
AI summary
The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.