Gate-All-Around Source/Drain Isolation for Lower DIBL Leakage
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices face challenges such as drain-induced-barrier-lowering (DIBL) issues and poor epitaxial source/drain (S/D) growth, leading to increased leakage current and mobility reduction, which degrade device performance.
Innovation Solution
The fabrication method involves forming epitaxial S/D features on a dielectric layer without direct contact with the substrate, using a sacrificial epitaxy structure that is later replaced by an inner spacer, thereby improving DIBL and leakage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial S/D structures directly contact the substrate in conventional GAA devices, then fabrication is simplified, but DIBL issues occur and leakage current increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the epitaxial S/D structures and the substrate. This dielectric layer prevents direct contact, thereby reducing drain-induced-barrier-lowering (DIBL) effects and controlling leakage current while maintaining fabrication feasibility through standard deposition processes.
Solution Approach 2:
The patent segments the direct contact interface between epitaxial S/D structures and substrate by inserting a dielectric layer. This segmentation creates distinct functional regions: the epitaxial S/D structures, the dielectric isolation layer, and the substrate, allowing independent optimization of each region's properties.
2Ease of manufacture
If epitaxial S/D structures directly contact the substrate, then manufacturing process is simpler, but device performance degrades due to DIBL
Solution Approach 1:
A dielectric layer is introduced as a mediator between the epitaxial S/D structures and the substrate. This intermediary layer reduces drain-induced-barrier-lowering (DIBL) effects, thereby improving device performance while maintaining compatibility with standard manufacturing processes.
Solution Approach 2:
The patent changes the physical parameter of the S/D-substrate interface by introducing a dielectric layer with specific electrical properties. This parameter change (from direct semiconductor-to-substrate contact to dielectric-isolated contact) reduces DIBL effects and improves overall device performance.
3Productivity
If epitaxial growth is performed directly on substrate, then process is faster, but poor epitaxial S/D growth occurs causing defects and mobility reduction
Solution Approach 1:
The patent performs preliminary preparation by forming a dielectric layer on the substrate before epitaxial growth. This preliminary action creates an optimized growth surface that enables high-quality epitaxial S/D structures with reduced defects and improved mobility, while the epitaxial growth process itself maintains high productivity.
Solution Approach 2:
The dielectric layer serves as an intermediary growth substrate that provides superior epitaxial growth conditions compared to direct substrate contact. This intermediary surface enables better crystal quality, reduced defects, and improved carrier mobility in the epitaxial S/D structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances GAA device performance by reducing defects and optimizing the S/D region, resulting in improved DIBL and reduced current leakage.
Implementation Method 1
epitaxial S/D features grown in the source/drain region of the fin
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer including different semiconductor materials, and the fin comprises a channel region and a source/drain region; forming a dummy gate structure over the channel region of the fin and over the substrate; etching a portion of the fin in the source/drain region to form a trench therein, wherein a bottom surface of the trench is below a bottom surface of the second semiconductor layer; selectively removing an edge portion of the second semiconductor layer in the channel region such that the second semiconductor layer is recessed; forming a sacrificial structure around the recessed second semiconductor layer and over the bottom surface of the trench; and epitaxially growing a source/drain feature in the source/drain region of the fin.