GAA Source/Drain Epitaxy for Uniform Core Layer Growth
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Solution Overview
Problem
As semiconductor devices shrink in size, they face challenges such as short channel effects, increased source/drain electron tunneling, and performance issues due to non-uniform growth of epitaxial layers in nanostructure transistors like GAA devices, leading to parasitic resistance and contact resistance.
Innovation Solution
A deposition recipe with a lower temperature and higher pressure is used to form a core epitaxial layer in the source/drain region of GAA devices, promoting uniform growth and reducing the likelihood of voids and defects, thereby decreasing parasitic resistance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition recipes are used to form epitaxial layers in source/drain regions, then deposition speed is maintained, but non-uniform growth and voids/defects occur leading to high parasitic resistance
Solution Approach 1:
The patent applies parameter changes by modifying deposition temperature and pressure parameters during epitaxial layer formation. Specifically, it uses a first deposition recipe with a first temperature and pressure to form an initial epitaxial layer, then switches to a second deposition recipe with a second lower temperature and second higher pressure to complete the epitaxial layer. This parameter transformation resolves the contradiction by achieving both uniform growth (improving manufacturing precision) and reducing voids/defects (improving reliability by reducing parasitic resistance).
Solution Approach 2:
The patent implements periodic action through multi-stage deposition processes. It performs deposition in distinct phases: first forming an initial epitaxial layer with conventional parameters, then switching to modified parameters for completing the layer. This periodic switching between deposition conditions allows the system to achieve uniform growth while preventing defect formation, thereby resolving the contradiction between manufacturing precision and reliability.
2Length of moving object
If gate length is reduced for smaller technology nodes, then device scaling is achieved, but source/drain electron tunneling increases leading to higher off current
Solution Approach 1:
The patent applies preliminary action by forming buffer regions and carefully controlling epitaxial layer formation in source/drain areas before final device operation. The multi-stage deposition process prepares the epitaxial layers with optimized uniformity and defect reduction in advance, which prevents electron tunneling issues when gate length is reduced. This preliminary preparation resolves the contradiction by addressing tunneling prevention before the scaling problem manifests.
Solution Approach 2:
The patent implements local quality by creating buffer regions with specific material compositions and properties in the source/drain areas adjacent to the channel. These localized regions have different characteristics from the main source/drain regions, providing graded transitions that reduce electron tunneling. This local modification allows device scaling (reduced gate length) while maintaining low off-current through localized quality adjustments at critical interfaces.
3Manufacturing precision
If deposition temperature is lowered and pressure is increased, then uniform growth and defect reduction are achieved, but deposition speed decreases
Solution Approach 1:
The patent resolves the speed-uniformity contradiction through periodic action by implementing multi-stage deposition with different parameter sets. The first stage uses conventional higher temperature and lower pressure for faster initial deposition, then switches to lower temperature and higher pressure for the final stages to achieve uniformity and defect reduction. This time-based switching allows the system to achieve both high productivity (through fast initial deposition) and high manufacturing precision (through careful final deposition).
Solution Approach 2:
The patent applies preliminary action by forming an initial epitaxial layer with conventional deposition parameters before switching to optimized parameters. This preliminary deposition establishes the base layer quickly, then the subsequent stages with lower temperature and higher pressure refine the structure for uniformity and defect reduction. This preliminary-fast-then-slow approach resolves the contradiction by achieving both productivity and manufacturing precision at different stages of the same process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of GAA devices by reducing parasitic resistance and contact resistance, improving yield and overall device performance.
Implementation Method 1
forming a first epitaxial layer at a bottom of the recess; selectively forming a combination of one or more seed layers on the first epitaxial layer and on ends of one or more of the plurality of channel layers; forming a second epitaxial layer on the combination of one or more seed layers and on spacers at ends of one or more of the plurality of sacrificial layers
Data Source
AI summary
Some implementations described herein include a semiconductor device including a gate-all-around transistor. The gate-all-around transistor includes a source/drain region having a core epitaxial layer and a capping epitaxial layer. The core epitaxial layer is formed within the source/drain region using a deposition recipe having a temperature that is lesser relative to temperatures of other deposition recipes used to form other epitaxial layers, including the capping layer, within the source/drain region. The deposition recipe further includes a pressure that is greater relative to pressures of the other deposition recipes used to form the other epitaxial layers within the source/drain region. The temperature and pressure of the deposition recipe used to form the core epitaxial layer promote a uniform growth of the core epitaxial layer within the source/drain region. In this way, a likelihood of voids and/or defects is reduced to increase a yield of a semiconductor device including the core epitaxial layer.