GAA Transistor Spacer Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) devices face challenges as they are not entirely satisfactory in all aspects, particularly in processing and manufacturing complexity as IC technologies progress towards smaller technology nodes.
Innovation Solution
The implementation of gate spacers and inner spacers with air gaps in GAA transistors, improving parasitic capacitance and transistor performance through advanced patterning techniques like double-patterning or multi-patterning processes, and the use of dielectric materials for isolation and gate replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing methods are used for GAA devices, then existing technologies can be maintained, but manufacturing complexity increases and performance improvement is limited as IC technologies progress towards smaller nodes
Solution Approach 1:
The gate structure is segmented into multiple components including gate spacers, inner spacers, and gate electrodes that wrap around the channel from all directions. This segmentation enables better control over the channel while distributing the manufacturing process into manageable stages, resolving the contradiction between achieving superior transistor performance and managing manufacturing complexity
Solution Approach 2:
The patent implements a nested structure where inner spacers are positioned within the gate spacer structure, and gate electrodes are wrapped around the channel in a nested configuration. This nesting approach maximizes the gate control area without proportionally increasing manufacturing complexity, as the nested components can be formed through sequential deposition and etching processes
2Area of moving object
If geometry size is decreased to increase functional density, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel in multiple dimensions. This dimensional change increases the effective gate control area without increasing the chip footprint, thereby maintaining manufacturing precision requirements while reducing the area needed for each functional unit
Solution Approach 2:
The gate structure implements local quality variations through different spacer materials and thicknesses in different regions. The inner spacers and outer gate spacers have different characteristics optimized for their specific functions, allowing precise control of electrical properties at different locations without requiring uniform high precision across the entire structure
3Area of stationary object
If gate-all-around structures are implemented to reduce chip footprint, then area is reduced, but parasitic capacitance increases
Solution Approach 1:
Dielectric materials are introduced as intermediary substances between the gate electrodes and the channel, and between adjacent gate structures. These intermediary dielectric layers electrically isolate the conductive gate elements, reducing parasitic capacitance coupling while maintaining the compact gate-all-around geometry that reduces chip footprint
Data Source
AI summary
A method for manufacturing a semiconductor structure includes forming a fin over a substrate. The fin includes first semiconductor layers and second semiconductor layers alternating stacked in a first direction. The method also includes forming a dummy gate structure over the fin, forming first gate spacers on opposite sides of the dummy gate structure in a second direction, forming source/drain features on opposite sides of the dummy gate structure in the second direction, replacing the dummy gate structure and the first semiconductor layers with a gate structure, replacing the first gate spacers with second gate spacers, and forming inner spacers between the second semiconductor layers in the first direction. The gate structure wraps around the first semiconductor layers. Each of the second gate spacers has a first air gap. Each of the inner gate spacers has a second air gap.