GAA Transistor Inner Spacer Embedding for Leakage and Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around nanowires is challenging due to limitations in current fabrication methods, which need further improvements to enhance gate control and reduce parasitic capacitance and leakage current.
Innovation Solution
The method involves forming inner spacers that are partially embedded in source/drain epitaxial structures, with a thicker inner spacer extending from the fin structure's sidewall, using a combination of photolithography and self-aligned processes to pattern the GAA structure, and depositing a second inner spacer to reduce parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used for GAA transistor integration, then manufacturing process compatibility is maintained, but gate control is insufficient and parasitic capacitance is high
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming first inner spacers, depositing source/drain epitaxial structures, forming second inner spacers, and creating gate structures. Each stage addresses specific requirements independently, allowing complex GAA transistor integration while maintaining conventional CMOS process compatibility.
Solution Approach 2:
Inner spacers are formed before the gate structure to pre-establish the necessary spacing and electrical isolation. This preliminary action reduces parasitic capacitance between the gate and source/drain regions before the gate is deposited, improving gate control without requiring complex post-processing.
2Object-affected harmful factors
If inner spacers are made thinner to reduce device dimensions, then area is reduced, but parasitic capacitance and leakage current increase
Solution Approach 1:
The inner spacer structure employs varying thicknesses at different locations: thicker regions provide enhanced electrical isolation and reduced parasitic capacitance where needed, while thinner regions maintain compact device dimensions. This localized quality variation optimizes both electrical performance and space utilization.
Solution Approach 2:
The structure implements nested spacers where inner spacers are positioned within the broader device architecture, with second inner spacers nested within the source/drain epitaxial structures. This nesting arrangement maximizes space utilization while maintaining adequate isolation distances to reduce parasitic capacitance.
3Object-generated harmful factors
If conventional spacer formation is used, then process simplicity is maintained, but leakage current between gate and source/drain structures is high
Solution Approach 1:
Inner spacers serve as intermediary structures between the gate and source/drain epitaxial structures, providing electrical isolation and preventing direct contact that would cause leakage current. These intermediary elements are integrated into the fabrication sequence without requiring fundamentally new process equipment or methods.
Data Source
AI summary
A semiconductor device structure includes a fin structure formed over a substrate. The structure also includes nanostructures formed over the fin structure. The structure also includes a gate structure wrapped around the nanostructures. The structure also includes a first inner spacer formed beside the gate structure. The structure also includes a second inner spacer formed beside the first inner spacer. The structure also includes spacer layers formed over opposite sides of the gate structure above the nanostructures. The structure also includes source/drain epitaxial structures formed over opposite sides of the fin structure. The second inner spacer is partially embedded in the source/drain epitaxial structures.