GAA Source/Drain Epitaxy Guided by Inner Spacer Formation
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Solution Overview
Problem
Existing GAA transistor fabrication technologies face challenges in forming inner spacers, leading to poor epitaxial growth and crystalline dislocation in source/drain regions, which affect the quality and integrity of the semiconductor device.
Innovation Solution
A method for forming gate-all-around transistors that includes forming inner spacers by depositing a dielectric layer between channel members, etching it back to create spacers, and using cyclic etching processes to maintain spacer integrity and improve epitaxial growth quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are formed using existing GAA fabrication technologies, then gate control is improved by increasing gate-channel coupling, but poor epitaxial growth and crystalline dislocation occur in source/drain regions
Solution Approach 1:
The method performs preliminary actions by forming the inner spacer structure before the source/drain epitaxial growth process. A dielectric material layer is deposited and patterned to create inner spacers that define the source/drain regions in advance, ensuring proper structural guidance for subsequent epitaxial growth and preventing crystalline dislocation.
Solution Approach 2:
The inner spacer structure acts as an intermediary element between the gate structure and the source/drain regions. The dielectric material layer serves as a mediator that enables controlled epitaxial growth by providing a proper interface and structural template, thereby improving both gate control and epitaxial growth quality simultaneously.
2Device complexity
If inner spacers are formed using existing GAA fabrication technologies, then device complexity is reduced by simplifying the fabrication process, but crystalline dislocation and poor epitaxial growth occur
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: first forming the inner spacer structure by depositing and patterning the dielectric material layer, then performing source/drain epitaxial growth, and finally removing the dielectric material layer. This segmentation allows each step to be optimized independently, maintaining crystalline integrity while managing fabrication complexity.
Solution Approach 2:
The method changes the temporal parameter of the dielectric material layer by introducing it as a temporary structure that is formed, used as a template, and then removed. This parameter change (temporary presence) enables precise control of epitaxial growth without permanently increasing device complexity, as the dielectric layer is eliminated after serving its guiding function.
3Reliability
If inner spacers are formed to reduce capacitance and prevent leakage, then device performance is improved, but poor epitaxial growth and crystalline dislocation occur in source/drain regions
Solution Approach 1:
The inner spacer structure is formed in advance before source/drain epitaxial growth, establishing proper structural boundaries and interfaces that guide the epitaxial growth process. This preliminary formation ensures both the performance benefits of reduced capacitance and prevention of leakage, while simultaneously ensuring high-quality epitaxial growth without crystalline dislocation.
Solution Approach 2:
The dielectric material layer serves as an intermediary template during the epitaxial growth process, providing a controlled interface that enables both the electrical performance benefits (reduced capacitance and leakage prevention) and the structural quality benefits (improved epitaxial growth without dislocation). The intermediary is then removed, leaving both performance and structural improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the quality of source/drain features by reducing voids and dislocations, ensuring accurate dimensions and positions of inner spacers, thereby improving the performance and reliability of GAA transistors.
Implementation Method 1
depositing a dielectric material layer wrapping around the channel members
Implementation Method 2
depositing a dielectric material layer wrapping around the channel members
Implementation Method 3
inner spacers interposing the metal gate structure and the source/drain features
Data Source
AI summary
A semiconductor structure includes nanostructures vertically stacked above a substrate, a gate structure wrapping around at least one of the nanostructures, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the nanostructures, and inner spacers interposing the source/drain feature and the gate structure. The source/drain feature includes a first epitaxial layer and a second epitaxial layer. A dopant concentration in the first epitaxial layer is less than a dopant concentration of the second epitaxial layer. The first epitaxial layer separates the second epitaxial layer from the nanostructures. The first epitaxial layer has a straight sidewall extending continuously from a sidewall of a topmost one of the nanostructures to a sidewall of a bottommost one of the nanostructures.