GAA Semiconductor Structure With Variable Spacer Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating high-density, high-speed, and high-voltage applications due to the complexity of scaling down IC processing and manufacturing, which requires advanced isolation structures to minimize current leakage and optimize gate dielectric thickness for both performance and voltage requirements.
Innovation Solution
The integration of gate-all-around (GAA) devices with improved isolation structures, including variations in gate pitches and inner spacers, allows for thinner or thicker spacers depending on the application, optimizing chip density and performance by reducing source/drain resistance and capacitance while enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around devices with varied inner spacers are used, then breakdown voltage is enhanced and source/drain resistance is reduced, but device structure and processing complexity increase
Solution Approach 1:
The patent applies local quality by implementing different inner spacer thicknesses in different regions of the semiconductor device. Specifically, first inner spacers with a first thickness and second inner spacers with a second thickness are used in different device regions, allowing optimization of breakdown voltage and source/drain resistance locally while managing overall device complexity through targeted structural variations rather than uniform design changes.
2Productivity
If scaling down process is used, then production efficiency increases and costs decrease, but power dissipation increases
Solution Approach 1:
The patent addresses the power dissipation issue arising from scaling down by changing key structural parameters: implementing gate-all-around devices with optimized channel dimensions and varied inner spacer thicknesses. These parameter changes enable better electrical control and reduced leakage currents, thereby lowering power dissipation while maintaining the benefits of scaled-down manufacturing for improved productivity and reduced costs.
3Speed
If thinner gate dielectric is used, then device performance improves, but voltage handling capability decreases
Solution Approach 1:
The patent resolves the contradiction between device performance and voltage handling by applying local quality through spatially varied inner spacer design. Thinner gate dielectric is used in regions where high-speed performance is critical, while thicker inner spacers are positioned in regions requiring enhanced voltage handling and isolation. This localized optimization allows each region to be tuned for its specific functional requirements without compromising overall device reliability.
Data Source
AI summary
A method includes forming first, second, third, and fourth semiconductive sheets over a substrate and arranged in a vertical direction; forming a first source/drain region between the first and second semiconductive sheets, and a second source/drain region between the third and fourth semiconductive sheets; forming a first gate around each of the first semiconductive sheets, a second gate around each of the second semiconductive sheets, a third gate around each of the third semiconductive sheets, and a fourth gate around each of the fourth semiconductive sheets, wherein the second gate pitch of the third and fourth gates is greater than the first gate pitch of the first and second gates; forming first spacers interleaving with the first semiconductive sheets, and second spacers interleaving with the third semiconductive sheets, wherein the second lateral dimension of the second spacers is greater than the first lateral dimension of the first spacers.