GAA Source/Drain Spacer Structure for Lower Parasitic Capacitance

Solution Overview

Problem

Existing gate-all-around (GAA) devices face challenges in reducing parasitic capacitance and preventing source/drain structure defects due to lateral merging, which hinders the scaling of IC technologies and affects transistor performance.

Innovation Solution

The use of sidewall spacers, promoted by an extra semiconductor layer, confines the lateral growth of source/drain structures, reducing parasitic capacitance and preventing defects, and allows for more room in gate trenches for patterning processes without relying on dielectric fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If source/drain structures are allowed to grow laterally to increase transistor density, then device integration improves, but parasitic capacitance increases and defects occur due to lateral merging

Engineering Contradiction:

Improvetransistor densityVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The source/drain structure is segmented into multiple discrete regions by introducing sacrificial nanosheet structures between them. This segmentation prevents lateral merging while maintaining high density, as each source/drain region is isolated by the sacrificial material that can be selectively removed to create gaps.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Sacrificial nanosheet structures are introduced as intermediary elements between source/drain regions. These intermediaries physically separate the source/drain structures during fabrication, preventing harmful lateral merging and reducing parasitic capacitance, while allowing the source/drain regions to be formed at high density.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If source/drain structures are allowed to grow laterally to increase transistor density, then device integration improves, but defects occur due to lateral merging

Engineering Contradiction:

Improvetransistor densityVSAvoiddefect prevention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The source/drain structure is segmented into multiple discrete regions by introducing sacrificial nanosheet structures between them. This segmentation prevents lateral merging while maintaining high density, as each source/drain region is isolated by the sacrificial material that can be selectively removed to create gaps.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Sacrificial nanosheet structures are introduced as intermediary elements between source/drain regions. These intermediaries physically separate the source/drain structures during fabrication, preventing harmful lateral merging and reducing parasitic capacitance, while allowing the source/drain regions to be formed at high density.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional fabrication processes are used for GAA devices, then manufacturing simplicity is maintained, but control over source/drain lateral growth and parasitic capacitance reduction is insufficient

Engineering Contradiction:

Improvefabrication process simplicityVSAvoidsource/drain lateral growth control

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

Sacrificial nanosheet structures are formed preliminarily before source/drain deposition. This preliminary action establishes the lateral boundaries for source/drain growth in advance, enabling precise control over lateral dimensions while using conventional fabrication processes for the subsequent steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention transitions from two-dimensional lateral source/drain formation to three-dimensional vertical stacking with sacrificial nanosheets. By adding the vertical dimension with interleaved sacrificial layers, precise lateral control is achieved without complicating the overall fabrication process.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12166075B2Method and structure for gate-all-around devices

Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.