Gate-All-Around Spacer Thickness Layout for I/O and Core Logic
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Solution Overview
Problem
The integration of gate-all-around I/O devices and core logic devices on a common semiconductor substrate is challenging due to their differing requirements, particularly in terms of channel length and gate dielectric thickness, which makes them susceptible to operating voltage and static discharge issues.
Innovation Solution
The semiconductor structure incorporates gate-all-around I/O devices with wider channel lengths and thicker dielectric and inner spacers compared to core logic devices, allowing for their integration on the same substrate while maintaining reliability by accommodating different operational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate-all-around I/O devices and core logic devices are integrated on a common semiconductor substrate, then device integration and area efficiency are improved, but reliability deteriorates due to conflicting requirements for channel length and gate dielectric thickness
Solution Approach 1:
The patent applies local quality by implementing different spacer thicknesses in different device regions. Specifically, I/O devices are equipped with thicker dielectric spacers and inner spacers compared to core logic devices. This local differentiation allows each device type to have optimized dimensions for its specific requirements, enabling both device types to coexist on the same substrate with appropriate voltage handling capabilities.
2Reliability
If I/O devices are designed with larger channel length and gate dielectric thickness, then reliability against static discharge is improved, but device complexity increases when integrating with core logic devices
Solution Approach 1:
The patent segments the semiconductor substrate into distinct I/O device regions and core logic device regions. Each region is independently optimized with appropriate spacer dimensions - thicker spacers in I/O regions for static discharge protection, and thinner spacers in core logic regions for voltage withstanding. This segmentation allows both device types to maintain their optimal design parameters without compromising the other.
Solution Approach 2:
Different spacer thicknesses are applied locally to different device regions. I/O devices receive thicker dielectric spacers and inner spacers for enhanced static discharge protection, while core logic devices use thinner spacers optimized for their voltage requirements. This local quality approach resolves the contradiction by allowing each device type to have its own optimized dimensions.
3Area of stationary object
If core logic devices use smaller channel length and gate dielectric thickness, then area efficiency is improved, but susceptibility to operating voltage increases
Solution Approach 1:
The patent implements local quality by providing core logic devices with thinner dielectric spacers and inner spacers optimized for their specific voltage requirements and compact dimensions. This localized optimization allows core logic devices to achieve high area efficiency while maintaining appropriate protection against operating voltage through dimensionally optimized spacers tailored to their smaller scale.
Data Source
AI summary
A semiconductor structure including a gate-all-around input/output (I/O) device and a gate-all-around core logic device integrated on a semiconductor substrate is provided. The gate-all-around I/O device, which has a wider channel length than the gate-all-around core logic device, has a dielectric spacer and/or inner spacers that is (are) laterally wider (i.e., thicker) than a dielectric spacer and/or inner spacers present in the gate-all-around core logic device.