GAA Inner Spacer Void Structure for Lower Gate Parasitic Capacitance
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in reducing parasitic capacitance between source/drain epitaxial features and high-k metal gates, which affects device performance and manufacturing complexity.
Innovation Solution
The method involves forming inner spacers with voids between source/drain epitaxial features and high-k metal gates, using a process that includes etching semiconductor layers to create gaps, depositing a dielectric layer that partially fills these gaps, and performing an etch-back process to maintain voids, thereby reducing parasitic capacitance and protecting the source/drain features during channel release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional GAA devices are used, then manufacturing process is simpler, but parasitic capacitance between source/drain epitaxial features and high-k metal gates is high
Solution Approach 1:
The patent divides the gap-filling process into multiple stages: initial deposition of dielectric material, selective removal to create voids, and controlled refill. This segmentation allows precise control over where dielectric material is present or absent, enabling reduction of parasitic capacitance in specific regions while maintaining structural integrity elsewhere.
Solution Approach 2:
The patent applies different dielectric properties to different regions: voids (air gaps) are created in regions where low parasitic capacitance is desired, while dielectric material is retained in regions providing mechanical support or electrical isolation. This local differentiation of dielectric quality directly addresses the parasitic capacitance issue without uniformly complicating the entire device structure.
2Object-generated harmful factors
If inner spacers with voids are formed, then parasitic capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary deposition of dielectric material that completely fills the gaps before any void creation. This preliminary action establishes a uniform baseline structure that can then be selectively modified. The etch-back process removes material only from specific regions, and subsequent refill operations add material back only where needed, making the complex steps manageable through this preliminary uniform deposition.
Solution Approach 2:
The dielectric material serves as an intermediary that can be added and removed controllably. By using this intermediary material that can be deposited and etched with good selectivity, the patent enables precise control over void formation and refill operations. The intermediary material facilitates the transition between different structural states without requiring direct manipulation of the semiconductor layers themselves.
3Productivity
If inner spacers are formed without voids, then manufacturing is easier, but parasitic capacitance remains high affecting device operating speed
Solution Approach 1:
The patent extracts dielectric material from specific regions to create voids between the inner spacers and source/drain epitaxial features. This extraction removes the source of parasitic capacitance in critical regions while maintaining the inner spacer structure for mechanical support and alignment. The selective removal enables high device operating speed by reducing capacitive coupling without completely eliminating the spacer structure.
Solution Approach 2:
The patent creates a porous structure with controlled voids rather than a solid continuous dielectric. These voids act as low-dielectric-constant regions that reduce parasitic capacitance. The porous configuration is achieved through controlled etching and refill processes that create a specific spatial distribution of voids and dielectric material optimized for electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, enhancing device operating speed and integrating seamlessly with existing semiconductor manufacturing processes while providing protection for source/drain features during etching.
Implementation Method 1
depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers
Implementation Method 2
etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap
Data Source
AI summary
A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.