Extra Inner Spacers in GAA Transistors for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices, such as horizontal gate-all-around (HGAA) transistors, suffer from excessive parasitic capacitance between the gate and source/drain, which degrades device performance.
Innovation Solution
The formation of extra inner spacers with a low-k dielectric material between the high-k dielectric layers and the gate structure, which increases the effective dielectric thickness and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HGAA device structure is used, then gate control is improved, but parasitic capacitance between gate and source/drain increases excessively
Solution Approach 1:
The patent introduces an intermediary dielectric layer between the gate electrode and the source/drain regions. This intermediate layer acts as a mediator that reduces the direct capacitive coupling between the gate and source/drain, thereby reducing parasitic capacitance while preserving the gate control benefits of the HGAA structure.
Solution Approach 2:
The patent extends the dielectric layer into the recess region between the gate and source/drain, utilizing the vertical dimension to reduce parasitic capacitance. By filling the recess area with dielectric material, the patent creates additional separation in the vertical dimension, effectively reducing the capacitive coupling without compromising the horizontal gate control.
2Reliability
If gate-all-around structure is implemented, then short-channel effects are reduced, but parasitic capacitance degrades device performance
Solution Approach 1:
The dielectric layer serves as a mediator that allows the HGAA structure to maintain its short-channel effects mitigation benefits while reducing parasitic capacitance. The intermediary layer is strategically positioned to reduce capacitive coupling without interfering with the gate's control over the channel.
Solution Approach 2:
The patent applies local quality by introducing the dielectric layer specifically in the recess region where parasitic capacitance occurs, while maintaining the conventional HGAA structure in the channel region. This localized modification reduces parasitic capacitance without compromising the overall gate control and short-channel effects mitigation.
3Object-generated harmful factors
If dielectric thickness is increased to reduce parasitic capacitance, then device performance improves, but device area increases
Solution Approach 1:
The patent utilizes the vertical dimension by extending the dielectric layer into the recess region, thereby reducing parasitic capacitance without increasing the lateral device area. This dimensional approach allows capacitance reduction while maintaining compact device footprint.
Solution Approach 2:
The dielectric layer is nested within the recess region formed during the HGAA fabrication process. By utilizing the existing recess space, the patent effectively increases the dielectric thickness for parasitic capacitance reduction without adding extra lateral dimensions or increasing the overall device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance, improving device performance, especially in high-frequency applications by increasing the dielectric thickness and utilizing low-k dielectric materials to minimize capacitance.
Implementation Method 1
conventional HGAA devices may have an excessive parasitic capacitance between the gate and the source/drain, which could adversely degrade device performance
Implementation Method 2
The formation of extra inner spacers with a low-k dielectric material between the high-k dielectric layers and the gate structure, which increases the effective dielectric thickness and reduces parasitic capacitance
Data Source
AI summary
A semiconductor device includes a plurality of nanostructures. The nanostructures each contain a semiconductive material. A plurality of first spacers circumferentially wrap around the nanostructures. A plurality of second spacers circumferentially wrap around the first spacers. A plurality of third spacers is disposed between the second spacers vertically. A gate structure surrounds the second spacers and the third spacers.