GAA SRAM Active Region Layout for Higher β Ratio Stability
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Solution Overview
Problem
Fin-based SRAMs, such as those using FinFETs, provide limited design flexibility for optimizing SRAM performance, particularly at scaled IC technology nodes, due to constraints on modifying physical dimensions to enhance read stability and write stability.
Innovation Solution
The use of gate-all-around (GAA) transistors in SRAM designs allows for greater flexibility in increasing or decreasing channel widths at scaled IC technology nodes, enabling optimization of the β ratio and threshold voltages of SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fin-based structures (FinFETs) are used to enhance SRAM performance at scaled IC technology nodes, then device performance is improved, but design flexibility for optimizing read stability and write stability is limited
Solution Approach 1:
The patent changes the transistor architecture from FinFET to GAA (gate-all-around) structure, enabling independent adjustment of channel widths for pull-down and pass-gate transistors. This parameter change provides the necessary design flexibility to optimize the beta ratio and threshold voltages for improved read and write stability while maintaining enhanced device performance at scaled technology nodes
2Reliability
If physical dimensions of FinFETs are modified to optimize SRAM performance, then read stability and write stability are improved, but design flexibility is constrained
Solution Approach 1:
The patent modifies the transistor architecture to GAA structure, which enables independent parameter adjustment of channel widths. This allows optimization of the beta ratio (ratio of pull-down to pass-gate transistor currents) and threshold voltages to improve read stability and write stability without the dimensional constraints that limit FinFET designs
3Reliability
If channel width of pull-down transistors is increased relative to pass-gate transistors, then beta ratio is enhanced and read stability is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar FinFET structure to three-dimensional GAA structure where the gate completely surrounds the channel. This dimensional change enables independent control of channel widths for pull-down and pass-gate transistors through selective placement of semiconductor nanowires, achieving enhanced beta ratio and read stability while managing device complexity through systematic structural organization
Data Source
AI summary
SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.