GAA SRAM and Logic Cell Layout With Width-Tuned Channel Stacks
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) transistors in integrated circuits (ICs) are complex and costly, and have not been entirely satisfactory for all applications, particularly in scaling down processes for smaller technology nodes.
Innovation Solution
The development of an IC structure that includes arrays of SRAM and standard logic cells with GAA FETs, featuring vertically stacked semiconductor layers and high-k metal gate structures, optimized channel layer widths, and dielectric fins to improve gate control and reduce leakage current, allowing for better scaling and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate-all-around transistors are incorporated into memory and core devices to reduce chip footprint, then device density is improved, but processing complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming sacrificial nanowires, depositing gate materials, removing sacrificial structures, and forming channel layers. This segmentation allows each complex step to be managed independently, reducing overall processing complexity while achieving gate-all-around structures that reduce chip footprint.
Solution Approach 2:
The patent employs preliminary actions by first forming sacrificial nanowire structures before depositing gate materials. These sacrificial structures serve as templates that guide subsequent processing steps, enabling precise formation of gate-all-around structures without requiring complex real-time control, thus reducing manufacturing complexity.
2Reliability
If vertically stacked semiconductor layers with high-k metal gate structures are used, then gate control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses sacrificial nanowire structures as intermediary elements that facilitate the formation of high-k metal gate structures. These intermediaries provide a simple template that enables complex gate-all-around architectures to be formed through sequential deposition and removal steps, improving gate control without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures by stacking semiconductor layers vertically. This dimensional change enables superior gate control over the channel from all directions, while the modular stacking approach allows systematic fabrication through repeated deposition cycles rather than complex single-step processes.
3Reliability
If channel layer widths are optimized in GAA NFETs and PFETs, then write margin is increased, but processing precision requirements increase
Solution Approach 1:
The patent optimizes channel layer width by controlling deposition parameters such as thickness, composition, and doping concentration during the formation of alternating semiconductor layers. By adjusting these parameters systematically, the patent achieves different effective channel widths for NFETs and PFETs to optimize write margin, while the sequential deposition process provides inherent control that reduces the stringency of final precision requirements.
Data Source
AI summary
An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.