GAA SRAM and Logic Transistor Layout for Smaller IC Footprints
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) transistors in semiconductor integrated circuits face challenges in complexity and cost, particularly in designing IC chips for multiple applications, where current methods are not entirely satisfactory.
Innovation Solution
The proposed solution involves an IC structure with arrays of SRAM and standard logic cells, each incorporating p-type and n-type three-dimensional fin-like active regions with vertically stacked semiconductor layers forming channel regions for GAA FETs, optimized for better gate control, reduced leakage current, and improved scaling capabilities, using high-k metal gate structures and specific fin configurations to balance carrier mobility and transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate-all-around transistors are incorporated into memory devices and core devices to reduce chip footprint, then device density is improved, but processing complexity and manufacturing cost increase
Solution Approach 1:
The channel region is segmented into multiple vertically stacked semiconductor layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) with different widths. This segmentation allows each layer to be independently optimized for specific functions: the narrower first and third layers provide better gate control for reduced leakage, while the wider second layer maintains carrier mobility, thus achieving high device density without proportionally increasing processing complexity
Solution Approach 2:
Different regions of the channel structure are assigned different local qualities through varying semiconductor layer widths. The first semiconductor layer has a first width, the second layer has a second width greater than the first, and the third layer has a third width greater than the second. This local quality variation enables simultaneous optimization of gate control (narrower layers) and carrier transport (wider layers) within the same transistor structure
2Area of moving object
If gate-all-around transistors are used to reduce chip footprint, then area efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The vertically stacked semiconductor layer structure serves multiple functions simultaneously: it provides the channel region for transistor operation, enables independent width optimization for different functional requirements, and maintains compatibility with existing fabrication processes. This multi-functionality achieves high device density without requiring entirely new manufacturing methodologies, thereby controlling manufacturing costs
3Object-generated harmful factors
If vertically stacked semiconductor layers with different widths are used to optimize gate control, then leakage current is reduced, but device structure complexity increases
Solution Approach 1:
The patent transitions from a planar two-dimensional channel structure to a three-dimensional vertically stacked structure with layers of varying widths. This dimensional change enables the gate to surround the channel region more completely, providing superior electrostatic control and reducing leakage current. The vertical stacking with different layer widths achieves this enhanced control while maintaining a relatively systematic structure that can be fabricated using extended conventional processes
Data Source
AI summary
An integrated circuit (IC) that includes a memory cell having a first p-type active region, a first n-type active region, a second n-type active region, and a second p-type active region. Each of the first and the second p-type active regions includes a first group of vertically stacked channel layers having a width W1, and each of the first and the second n-type active regions includes a second group of vertically stacked channel layers having a width W2, where W2 is less than W1. The IC structure further includes a standard logic cell having a third n-type fin and a third p-type fin. The third n-type fin includes a third group of vertically stacked channel layers having a width W3, and the third p-type fin includes a fourth group of vertically stacked channel layers having a width W4, where W3 is greater than or equal to W4.