GAA Stressor Layer Layout for NMOS and PMOS Mobility Control
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Solution Overview
Problem
Existing multigate devices, such as GAA devices, face challenges in achieving desired gate density and performance due to the complexity of integrating different stress requirements for NMOS and PMOS devices, which are not adequately addressed by current fabrication methods.
Innovation Solution
The method involves forming stressor layers during multigate device fabrication to provide separate stressor profiles for NMOS and PMOS devices, allowing independent control of stress distribution and direction to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate stressor layers are formed for NMOS and PMOS devices, then carrier mobility and device performance are improved, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent divides the stressor structure into separate first and second stressor layers, where the first stressor layer is formed adjacent to NMOS devices and the second stressor layer is formed adjacent to PMOS devices. This segmentation allows independent stress optimization for each device type, improving carrier mobility and device performance while maintaining manageable fabrication complexity through systematic process steps.
Solution Approach 2:
The patent applies different stress characteristics to different regions of the device structure. The first stressor layer provides stress optimized for NMOS devices, while the second stressor layer provides stress optimized for PMOS devices. This local quality approach ensures that each device type receives the appropriate stress profile for optimal performance without compromising the other device type.
2Reliability
If multigate device scaling is continued, then gate control and short-channel effect mitigation are improved, but achieving desired gate density and performance becomes more difficult
Solution Approach 1:
The patent transitions from planar stressor configurations to three-dimensional stressor layers that wrap around the channel region in multiple directions. The first and second stressor layers are positioned to provide stress from different spatial dimensions, enabling effective stress application in scaled multigate devices while maintaining gate control and improving gate density through vertical and lateral integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and overall device performance by applying tailored stress profiles to NMOS and PMOS devices, addressing the challenges of integrating different stress requirements and enhancing gate control.
Implementation Method 1
Stress distorts or strains the materials such as the semiconductor crystal lattice, and the distortion in turn affects the band alignment and charge transport properties of the material
Data Source
AI summary
Devices providing tensile/compressive stressor layers for gate-all-around devices. A first GAA device and a second GAA are disposed having a shallow trench isolation feature and one of more stressor layers between gate structures of the first GAA device and the second GAA. The stressor layers can provide tensile stress to a channel layer of the first GAA device and a compressive stress to another channel layer of the second GAA device.