GAA Source/Drain Stressor Removal for Low-Capacitance Contacts
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Solution Overview
Problem
In the development of gate-all-around field effect transistors (GAA FETs), achieving sufficient stress in the source/drain region while minimizing junction capacitance and leakage is challenging, especially as transistor dimensions are scaled down, due to the difficulty in balancing stress application and contact resistance.
Innovation Solution
A two-step process is employed, where a stressor layer is formed in the source/drain region before the metal gate structure is formed, and then removed after the metal gate is formed, maintaining the stress applied to the channel regions. This process includes pre-metal gate formation for stress tuning and post-metal gate formation for reducing junction capacitance and creating a low resistance path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stressor layer is formed in the source/drain region to apply stress to the channel, then device performance is improved, but junction capacitance and leakage increase
Solution Approach 1:
The source/drain region is segmented into multiple portions with different stressor layer configurations. First source/drain regions have stressor layers applied, while second source/drain regions have stressor layers removed or not applied, allowing differential stress application that improves performance while controlling parasitic effects.
Solution Approach 2:
Different regions of the source/drain structure are given different properties: some regions have stressor layers for stress application, while other regions have stressor layers removed to minimize junction capacitance. This local differentiation allows simultaneous optimization of stress benefits and parasitic reduction.
2Stress or pressure
If the stressor layer is retained in the source/drain region, then stress is maintained on the channel, but contact resistance increases
Solution Approach 1:
The source/drain region is divided into segments where stressor layers are selectively removed from contact portions while retained in other portions. This segmentation allows the channel region to maintain stress for performance while contact regions have reduced stressor layers to minimize contact resistance.
Solution Approach 2:
The stressor layer is extracted or removed from specific source/drain regions where it would otherwise increase contact resistance. This selective removal maintains the necessary stress on the channel while eliminating the harmful contact resistance effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces junction capacitance and contact resistance, improving device performance by maintaining stress on the channel regions while minimizing leakage and parasitic transistor effects.
Implementation Method 1
a stressor layer is formed in the source/drain region... a stressor layer including a semiconductor material having a lattice constant different from the second semiconductor layers
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.