GAA Semiconductor Structure With Sacrificial Fill for Dummy Gate Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around silicon nanowires in semiconductor manufacturing is challenging, leading to complexity and reduced manufacturing yield due to risks of dummy gate structure collapse and exposure of lower fin elements, which affects the reliability and performance of the resulting semiconductor devices.
Innovation Solution
A method involving the formation of a sacrificial material and protection layers over an isolation structure to prevent serious recessing during etching processes, thereby protecting the isolation structure and reducing the risk of dummy gate collapse and exposure of lower fin elements, ensuring reliable and efficient semiconductor structure formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form GAA features around silicon nanowires, then manufacturing complexity increases and yield decreases, but device performance cannot be achieved without these processes
Solution Approach 1:
The patent applies preliminary action by forming protection layers and sacrificial materials before the etching process. The isolation structure is prepared with protective coatings in advance, and sacrificial materials are deposited to prevent damage during subsequent etching operations. This preliminary preparation eliminates the need for complex in-process adjustments and reduces yield loss from dummy gate collapse.
Solution Approach 2:
The patent uses sacrificial materials as intermediary substances that mediate between the etching process and the isolation structure. These sacrificial materials are deposited over the isolation structure and dummy gates, serving as a protective intermediary layer that prevents direct contact between aggressive etchants and sensitive structures, thereby preventing collapse without adding permanent complexity to the device.
2Manufacturing precision
If aggressive etching is performed to form source/drain recesses, then manufacturing precision improves, but dummy gate structures collapse and lower fin elements are exposed
Solution Approach 1:
The patent implements beforehand cushioning by depositing protection layers and sacrificial materials prior to the aggressive etching process. These layers act as a cushion that absorbs the mechanical and chemical stress of the etching process, preventing direct damage to the dummy gate structures and lower fin elements. The sacrificial materials are specifically designed to withstand the etching conditions while protecting underlying structures.
Solution Approach 2:
Protection layers serve as an intermediary barrier between the aggressive etching environment and the sensitive dummy gate structures. This intermediary layer allows the etching process to proceed with high precision while preventing the collapse of dummy gates and exposure of lower fin elements by absorbing the harmful effects of the etchant.
3Reliability
If protection layers and sacrificial materials are formed over isolation structure, then dummy gate collapse is prevented, but additional manufacturing steps are required
Solution Approach 1:
The protection layers and sacrificial materials serve multiple functions simultaneously: they protect the isolation structure during etching, prevent dummy gate collapse, and provide a template for subsequent source/drain formation. This multi-functionality reduces the need for separate dedicated protection steps, thereby limiting the increase in manufacturing complexity while achieving reliable dummy gate stabilization.
Solution Approach 2:
The sacrificial materials are deposited to protect structures during critical etching steps, then selectively removed afterward. This temporary protection approach allows the use of aggressive etching processes for high precision source/drain formation while maintaining dummy gate stability. The sacrificial materials are discarded after serving their protective function, avoiding permanent addition of complex structures to the device.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming active regions over a substrate, forming an isolation structure to surround lower portions of the active regions, forming dummy gate structures across the active regions and the isolation structure, forming a spacer layer along the dummy gate structures, the active regions and the isolation structure to partially fill a space defined by the active regions and the dummy gate structures, forming a sacrificial material over the spacer layer to overfill a remainder of the space, recessing the sacrificial material to expose the spacer layer, etching the spacer layer to expose the active region, etching the active region to form a recess, and forming a source/drain feature in the source/drain recess.