GAA Nanowire Sub-Fin Contact Structure for IPC and ESD Dissipation
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Solution Overview
Problem
The challenge in fabricating nanowire transistors is the lack of electrical contact between the active transistor semiconductor and the underlying silicon substrate, which hinders charge dissipation during in-process charging (IPC) and electrostatic discharge (ESD) events.
Innovation Solution
The approach involves fabricating silicon (Si) or silicon germanium (SiGe) islands through pattern/etch/regrow processing, allowing for a conduction path to the underlying substrate during nanowire or nanoribbon formation. This method ensures proper protection of transistors during IPC and ESD events by providing a substrate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanowire transistors are fabricated without substrate contact, then device density and scaling are improved, but charge dissipation capability during IPC and ESD events deteriorates
Solution Approach 1:
The substrate contact structure is segmented into discrete fin regions that are selectively formed in specific areas beneath the nanowire transistor. This segmentation allows the nanowire transistor to maintain its isolated architecture for high density while providing localized substrate contact regions for charge dissipation, thus resolving the contradiction between device density and charge dissipation capability
Solution Approach 2:
The fin structure acts as an intermediary element between the nanowire transistor channel and the semiconductor substrate. The fin provides a conductive pathway that enables charge dissipation to the substrate without requiring direct contact between the nanowire channel and substrate, thereby maintaining both high device density and reliable charge dissipation
2Productivity
If lithographic features are scaled to smaller dimensions, then device capacity increases, but the spacing between features and manufacturing constraints worsen
Solution Approach 1:
The invention transitions from two-dimensional planar feature arrangement to three-dimensional vertical fin structures. By utilizing the vertical dimension for substrate contact, the lithographic constraints on lateral feature spacing are relaxed, enabling higher device capacity while maintaining manufacturable feature dimensions and spacing
Data Source
AI summary
Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.