Gate-All-Around Nanowire Substrate Contact Using Adjacent Deep Vias
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Solution Overview
Problem
The challenge in integrated circuit manufacturing lies in providing a reliable electrical contact between nanowire or nanoribbon transistors and the underlying silicon substrate to dissipate charge during in-process charging and electrostatic discharge events, as conventional solutions for bulk finFET transistors do not translate to nanowire or nanoribbon architectures.
Innovation Solution
The introduction of a deep via substrate contact is implemented to create a connection between NMOS or PMOS nanowires or nanoribbons and the silicon substrate, allowing for charge dissipation, which involves patterning and etching operations to form a conductive contact on the substrate, optionally filled with a conductive material, and can coincide with or be separate from the source/drain/gate structures, ensuring proper transistor protection during IPC and ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bulk finFET transistor structures are used, then manufacturing simplicity and cost-effectiveness are maintained, but nanowire or nanoribbon transistors cannot achieve proper substrate contact for charge dissipation
Solution Approach 1:
The patent introduces a vertical deep via structure that extends through the substrate to establish substrate contact, moving from a planar contact approach to a three-dimensional vertical contact approach. This allows nanowire transistors to achieve proper substrate contact for charge dissipation without fundamentally changing the transistor channel structure itself.
Solution Approach 2:
The patent introduces an intermediate deep via structure that serves as a mediator between the nanowire transistor and the substrate. This via structure, filled with conductive material, acts as a bridge to enable charge dissipation pathways that were previously unavailable in conventional nanowire transistor configurations.
2Reliability
If deep via substrate contact is implemented for nanowire transistors, then charge dissipation and circuit reliability are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent implements preliminary actions by forming the deep via structure and filling it with conductive material during the front-end-of-line (FEOL) manufacturing process, before subsequent interconnect layers are deposited. This early establishment of substrate contact ensures reliability is built into the structure from the outset, avoiding the need for complex retroactive modifications.
3Productivity
If feature dimensions are scaled down to increase device density, then capacity is improved, but maintaining substrate contact and charge dissipation becomes increasingly difficult
Solution Approach 1:
The patent addresses scaling challenges by transitioning from lateral contact approaches to vertical deep via contacts. This dimensional change allows substrate contact to be established independently of the lateral feature size, maintaining reliable charge dissipation pathways even as device dimensions are reduced to increase density.
Data Source
AI summary
Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.