GAA Substrate Isolation Structure for Junction Leakage Control
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Solution Overview
Problem
Multi-gate devices, particularly gate-all-around (GAA) devices, face challenges such as junction leakage and latch-up issues due to direct contact between epitaxial source/drain features and the substrate, which degrades their performance.
Innovation Solution
An anti-punch through (APT) layer is formed between the substrate and epitaxial source/drain features, isolated by a substrate isolation layer, with a higher dopant concentration than the substrate, extending under the epitaxial source/drain features and gate structure, mitigating direct contact and using a bulk Si substrate to reduce fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial source/drain features directly contact the substrate, then fabrication is simpler, but junction leakage and latch-up issues occur
Solution Approach 1:
An anti-punch through (APT) layer is introduced as an intermediary between the substrate and epitaxial source/drain features. This APT layer extends under the epitaxial S/D features and gate structure, preventing direct contact while maintaining fabrication compatibility. The isolation layer further mediates by separating the APT layer from the substrate, eliminating junction leakage and latch-up issues without significantly complicating the fabrication process.
2Reliability
If an APT layer and isolation layer are added to prevent direct contact, then junction leakage and latch-up issues are reduced, but device complexity increases
Solution Approach 1:
The APT layer and isolation layer are merged into a unified structure where the isolation layer simultaneously serves as both an electrical isolation medium and a structural support element. The APT layer is integrated beneath the existing epitaxial S/D features and gate structure, combining multiple functions into a compact arrangement that minimizes overall device complexity while effectively preventing junction leakage and latch-up.
3Ease of manufacture
If bulk Si substrate is used instead of specialized substrates, then fabrication costs are reduced, but substrate isolation performance may be compromised
Solution Approach 1:
The isolation layer acts as an intermediary that compensates for the lower intrinsic isolation performance of bulk Si substrates. By introducing this dedicated isolation layer between the substrate and the APT layer, the system achieves effective electrical isolation using cost-effective bulk Si substrates, thereby maintaining both cost efficiency and isolation performance.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.