Horizontal GAA Transistor Structure for APT Diffusion Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing bottom sheet threshold voltage shift and junction leakage due to anti-punch through (APT) doping diffusion during the fabrication of gate all-around (GAA) transistors, particularly at the 5 nm technology node and below.
Innovation Solution
The integration of horizontal gate-all-around nanostructure transistors involves a multi-layer stack with varying thicknesses of semiconductor materials, where a thicker bottommost layer prevents APT dopant diffusion into overlying layers, and a series of implantation steps with specific dopant concentrations to mitigate APT effects, allowing for a guard band and shallow source/drain depths to control threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-punch through (APT) doping is applied to prevent punch-through effects, then device reliability is improved, but bottom sheet threshold voltage shift and junction leakage worsen
Solution Approach 1:
The semiconductor structure is divided into multiple distinct layers with different doping concentrations. The bottommost layer has a first doping concentration while overlying layers have a second doping concentration, creating segmented doping regions that prevent harmful dopant diffusion while maintaining device reliability
Solution Approach 2:
Different regions of the semiconductor structure are assigned different doping concentrations tailored to their specific functional requirements. The bottommost layer receives a higher doping concentration to prevent punch-through, while overlying layers receive a lower concentration to minimize threshold voltage shift and junction leakage
2Productivity
If minimum feature size is reduced to increase integration density, then productivity is improved, but manufacturing precision and device performance worsen
Solution Approach 1:
The patent transitions from planar device architecture to vertically stacked three-dimensional structures. By stacking multiple semiconductor layers vertically, the design achieves higher integration density without further reducing the lateral minimum feature size, thereby maintaining manufacturing precision while improving productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates APT-induced issues, such as bottom sheet threshold voltage shift and junction leakage, while maintaining control over threshold voltage, thereby enhancing the performance and reliability of GAA transistors.
Implementation Method 1
prevents APT dopant diffusion into overlying layers
Implementation Method 2
a series of implantation steps with specific dopant concentrations
Data Source
AI summary
Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source/drain depths, and/or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.