GAA Transistor Structure With Backside Vias for Routing Space
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Solution Overview
Problem
The challenge of scaling down semiconductor IC dimensions has introduced increased complexity to the manufacturing process, necessitating advancements in semiconductor manufacturing processes to support smaller, faster, and more complex electronic devices.
Innovation Solution
The fabrication of gate-all-around (GAA) transistors with backside vias connected to the source regions, utilizing multi-gate devices like nanosheet transistors with gate structures on multiple sides of the channel region, and incorporating backside power rails to enhance electrostatic control and mitigate leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used, then manufacturing process is simpler, but electrostatic control over the channel is insufficient and leakage currents increase
Solution Approach 1:
The patent transitions from planar 2D gate control to 3D gate-all-around control by wrapping the gate structure completely around the channel region. This dimensional change enables the gate to control the channel from top, bottom, and sidewalls simultaneously, dramatically improving electrostatic control and reducing leakage currents while managing the increased structural complexity.
Solution Approach 2:
The gate structure is nested around the channel region in a concentric arrangement, with the gate completely surrounding the channel. This nested configuration allows maximum gate control over the channel with minimal space requirement, achieving superior electrostatic control without proportionally increasing device footprint.
2Area of stationary object
If front-side routing is used exclusively, then routing space is limited, but backside via fabrication adds process complexity
Solution Approach 1:
The patent utilizes the third dimension (backside of the substrate) for routing by forming vias through the substrate thickness. This vertical dimension expansion provides additional routing space without increasing planar area, effectively doubling the available routing real estate while adding via formation steps to the fabrication process.
Solution Approach 2:
The routing function is segmented between front-side and back-side of the substrate. Critical signals that require additional routing space are routed through backside vias, while other signals remain on the front side. This segmentation allows optimization of routing paths without requiring all connections to use the more complex backside via approach.
Data Source
AI summary
A device includes a channel structure, a gate structure, a first source/drain structure, a second source/drain structure, a backside via, a semiconductor structure, and a dielectric layer. The gate structure covers the channel structure. The gate structure includes a gate dielectric layer and at least one metal layer over the gate dielectric layer. The first source/drain structure and the second source/drain structure are on opposite sides and adjacent to sidewalls of the channel structure. The backside via is under the first source/drain structure. The semiconductor structure is under the second source/drain structure. The dielectric layer surrounds the backside via and under the semiconductor structure.