Fork-Like GAA Transistor Structure to Cut Capacitance and Bridging
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down transistor sizes while maintaining device density and performance, particularly in preventing gate-to-source/drain bridging and reducing device capacitance in nanostructure transistors.
Innovation Solution
The implementation of a gate-all-around (GAA) transistor structure with a fork-like nanostructure design, where nanostructure channels are surrounded by a gate electrode, and the use of dielectric materials with different etch selectivity to replace high-k dielectric layers, reducing device capacitance and avoiding gate-to-source/drain bridging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-k dielectric layers are used to improve transistor performance, then device performance is improved, but device capacitance increases
Solution Approach 1:
The patent applies local quality by using high-k dielectric material selectively in the gate all-around structure where high electric field control is needed, while using low-k dielectric material in the source/drain region where low capacitance is critical. This spatial differentiation of dielectric properties allows simultaneous optimization of transistor performance and capacitance reduction.
Solution Approach 2:
The patent employs composite materials by combining high-k dielectric layers with low-k dielectric materials in a multi-layer structure. The high-k dielectric provides superior gate control, while the low-k dielectric provides electrical isolation and low capacitance, creating a composite structure that achieves both high performance and low capacitance.
2Quantity of substance
If device size is reduced to increase device density, then device density increases, but gate-to-source/drain bridging occurs
Solution Approach 1:
The patent applies the nested doll principle through the gate all-around structure where the gate electrode completely surrounds the nanosheet channel, with the low-k dielectric material nested between the gate and the source/drain regions. This nested configuration provides physical separation that prevents bridging while maintaining high device density.
Solution Approach 2:
The low-k dielectric material serves as an intermediary element between the gate structure and the source/drain regions. This intermediary layer provides electrical isolation and physical separation, preventing direct contact and potential bridging between gate and source/drain while enabling closer spacing for higher density.
3Ease of manufacture
If conventional transistor structures are used to simplify manufacturing, then manufacturing is easier, but device density and scalability are limited
Solution Approach 1:
The patent transitions from planar transistor structures to a three-dimensional gate all-around configuration. The gate electrode wraps around the nanosheet channel in multiple dimensions, enabling superior control and higher density. This dimensional change is achieved through sequential deposition and etching processes that build the multi-layer structure vertically and then pattern it horizontally.
Solution Approach 2:
The patent applies segmentation by dividing the transistor into distinct functional regions: the nanosheet channel segment, the gate all-around electrode segments, the high-k dielectric segments, and the low-k dielectric segments. This segmentation allows each component to be optimized independently and facilitates modular manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved gate control over nanostructure channels, increased device density, and reduced manufacturing costs by minimizing gate-to-source/drain bridging and capacitance, enhancing performance scalability.
Implementation Method 1
a gate electrode surrounding the nanostructure channels
Implementation Method 2
the use of dielectric materials with different etch selectivity to replace high-k dielectric layers
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.