GAA Transistor Channel Extensions for Low Resistance and Capacitance
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing is to simultaneously achieve low resistance and low capacitance in gate-all-around (GAA) transistors, which are essential for different IC functions but difficult to achieve with a single fabrication process.
Innovation Solution
The solution involves selectively manufacturing GAA transistors with different attributes in different areas of a single substrate by varying the deposition of undoped silicon channel extension features, adjusting the thickness of top gate spacers, and reducing the thickness of spacer features after channel member release.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single type of GAA transistor is fabricated to perform all functions, then manufacturing cost is reduced, but performance or energy efficiency is sacrificed
Solution Approach 1:
The patent applies local quality by creating different GAA transistor types in different regions of the same substrate. First GAA transistors with first channel members are formed in a first region, while second GAA transistors with second channel members are formed in a second region. This allows each region to be optimized for specific functions (e.g., low resistance vs. low capacitance) while using a unified fabrication process, thus reducing manufacturing cost without sacrificing overall device performance
Solution Approach 2:
The substrate is segmented into multiple regions with different transistor characteristics. The fabrication process is divided into sequential steps where channel members are formed with different properties in different regions. This segmentation enables the circuit to have both high-performance transistors for critical functions and low-power transistors for non-critical functions, achieving a balance between cost and performance
2Productivity
If GAA transistors are scaled down to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent employs a universal fabrication process that can produce multiple types of GAA transistors simultaneously. The same deposition and patterning steps create both first channel members and second channel members with different characteristics. This multi-functional approach allows scaling down to increase functional density while avoiding the need for separate fabrication lines, thus managing processing complexity
Data Source
AI summary
Semiconductor structures and methods of fabrication are provided. A method according to the present disclosure includes receiving a workpiece that includes an active region over a substrate and having first semiconductor layers interleaved by second semiconductor layers, and a dummy gate stack over a channel region of the active region, etching source/drain regions of the active region to form source/drain trenches that expose sidewalls of the active region, selectively and partially etching second semiconductor layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming channel extension features on exposed sidewalls of the first semiconductor layers, forming source/drain features over the source/drain trenches, removing the dummy gate stack, selectively removing the second semiconductor layers to form nanostructures in the channel region, forming a gate structure to wrap around each of the nanostructures. The channel extension features include undoped silicon.