GAA Transistor Channel Structure for Higher Mobility in Compact FETs
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving high performance and compact size due to limitations in channel size and carrier mobility, particularly in gate-all-around (GAA) transistor structures.
Innovation Solution
The method involves forming a gate-all-around (GAA) field-effect transistor (FET) device with embedded and sidewall channel structures, where epitaxial layers and caps are patterned to create a multi-layered structure with dielectric fins and a replacement gate, enhancing channel size and carrier mobility while maintaining a compact device footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional planar transistor structure is used, then device fabrication is simpler, but carrier mobility and driving current are limited
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a 3D gate-all-around structure where the gate electrode completely surrounds the channel in three dimensions. This dimensional change enables the gate to control carrier flow from top, bottom, and sidewalls simultaneously, significantly enhancing carrier mobility and driving current while managing the increased structural complexity through systematic fabrication processes.
2Reliability
If channel size is increased to improve performance, then device volume increases
Solution Approach 1:
The gate electrode is nested around the channel in a gate-all-around configuration, with the gate wrapping completely around the channel structure. This nesting approach allows the channel to be positioned within the gate's controlling field from all directions, maximizing the effective channel utilization and driving current without requiring additional device footprint or volume, thereby achieving high performance in a compact form factor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases channel size for higher performance and driving current, while maintaining a small device volume, and can enhance carrier mobility by utilizing different crystal orientations for specific types of devices, such as P-type devices.
Implementation Method 1
forming an epitaxial stack on a substrate; forming an epitaxial cap covering the epitaxial stack; patterning the epitaxial stack and the epitaxial cap to form an embedded channel structure and a sidewall channel structure
Data Source
AI summary
A semiconductor device including an embedded channel structure, a sidewall channel structure and a gate electrode structure is provided. The embedded channel structure is disposed on a substrate. The sidewall channel structure is disposed on the substrate, and located at a lateral side of the embedded channel structure. The gate electrode structure is disposed on the substrate, encircles the embedded channel structure and is located between the embedded channel structure and the sidewall channel structure.