GAA Transistor Channel Thickness Tuning for Higher Drive Current
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in achieving efficient scaling and performance enhancement due to limitations in channel thickness and material selectivity, which affect driving current and device performance.
Innovation Solution
The implementation of gate all around (GAA) transistor structures with channels of varying thicknesses, formed through epitaxial layers with controlled deposition times, and patterned using photolithography and self-aligned processes, allowing for tuned driving currents and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If channel thickness is reduced to achieve scaling, then device density increases, but driving current decreases
Solution Approach 1:
The patent applies local quality by creating channel layers with different thicknesses within the same device structure. Specifically, first channel layers have a first thickness while second channel layers have a second thickness that is less than the first thickness. This allows different regions of the channel to have optimized properties: thicker regions provide higher driving current while thinner regions increase device density and scaling capability.
2Manufacturing precision
If material selectivity is improved for precise channel formation, then manufacturing precision increases, but process complexity increases
Solution Approach 1:
The patent employs parameter changes by varying deposition conditions during epitaxial growth to achieve different channel layer thicknesses. By adjusting epitaxial deposition parameters such as deposition time, temperature, or precursor flow rates, the process creates channel layers with precisely controlled different thicknesses without requiring additional complex processing steps.
3Power
If varying channel thicknesses are implemented to tune driving current, then device performance improves, but structural complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the channel structure into multiple discrete channel layers with different thicknesses. The channel comprises first channel layers and second channel layers, each with specific thickness characteristics. This segmentation allows independent optimization of each layer's contribution to driving current while maintaining overall structural organization through the gate all-around configuration.
Solution Approach 2:
The patent utilizes another dimension by implementing vertical stacking of channel layers with varying thicknesses in the thickness dimension. This vertical arrangement allows tuning of driving current through the cumulative effect of multiple layers, where thicker layers contribute more to current while the overall stacked structure achieves higher density. The gate structure wraps around all layers, creating a three-dimensional configuration that optimizes both performance and scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The GAA transistor structures enable enhanced driving currents and improved device performance by allowing for precise control of channel thickness and material selectivity, addressing the limitations of traditional scaling methods.
Implementation Method 1
forming an epitaxial stack over a substrate. The epitaxial stack includes a first sacrificial layer, a first channel layer, a second sacrificial layer, and a second channel layer sequentially over the substrate
Implementation Method 2
formed through epitaxial layers with controlled deposition times
Data Source
AI summary
A device includes a first channel structure, a second channel structure, a gate structure, source/drain structures, and a gate spacer. The second channel structure is over the first channel structure. A bottom surface of the first channel structure has a concave profile different from a concave profile of a bottom surface of the second channel structure. The gate structure wraps around the first channel structure and the second channel structure. The gate structure includes a gate dielectric layer and at least one metal layer over the gate dielectric layer. The source/drain structures are connected to the first channel structure and the second channel structure and on opposite sides of the gate structure. The gate spacer is between the gate structure and one of the source/drain structures. The gate spacer extends along a sidewall of the gate structure and in contact with the second channel structure.