GAA Nanostructure Transistor Contacts for Higher Driving Current
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Solution Overview
Problem
Existing nanostructure transistors have limited contact area between channel layers and source/drain structures, which restricts performance improvement due to limited contact faces, hindering increased driving current potential.
Innovation Solution
The development of a gate-all-around (GAA) field-effect-transistor (FET) device with a source/drain structure that contacts the channel layers through their sidewalls, top surfaces, and bottom surfaces, increasing the contact area by wrapping a gate structure around the full perimeter of nanostructure channels and using spacers and inner spacers to enhance contact points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar transistor architecture is used, then manufacturing is simpler, but contact area between source/drain and channel is limited
Solution Approach 1:
The patent transitions from planar 2D contact to 3D gate-all-around structure where the gate wraps completely around the channel, providing contact from top, bottom, and sidewalls. This dimensional change dramatically increases the effective contact area between source/drain structures and channel layers, enabling superior electrical performance while maintaining manufacturability through established semiconductor fabrication processes
2Area of stationary object
If minimum feature size is reduced to increase integration density, then more components fit in given area, but contact area between source/drain and channel decreases
Solution Approach 1:
By implementing gate-all-around architecture, the patent enables the channel to be contacted from multiple directions (top, bottom, sidewalls) rather than just planar contact. This allows the device footprint to be minimized for high integration density while the effective contact area is maximized through the three-dimensional gate structure wrapping around the channel
Solution Approach 2:
The gate structure is nested around the channel in a concentric arrangement, with the gate completely surrounding the channel cross-section. This nested configuration enables maximum contact area within the smallest possible footprint, allowing multiple such structures to be packed densely on the substrate while each individual device maintains large contact area
Data Source
AI summary
A semiconductor device includes a plurality of channel layers vertically spaced from one another. The semiconductor device includes a gate structure wrapping around each of the plurality of channel layers. The semiconductor device includes an epitaxial structure electrically coupled to the plurality of channel layers. The epitaxial structure contacts a sidewall, a portion of a top surface, and a portion of a bottom surface of each of the plurality of channel layers.