GAA Transistor Contact Layout for Lower Capacitance and Leakage
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity and the need for advanced manufacturing processes to achieve high-performance and low-power integrated circuits, while maintaining cost efficiency and miniaturization.
Innovation Solution
The method involves forming a gate-all-around (GAA) transistor structure with a sacrificial layer and spacers, using double-patterning or multi-patterning processes to create smaller pitches, and an additional conductive layer on the gate electrode that protrudes above the source/drain contact structure, reducing unwanted capacitance and leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into multiple discrete steps including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows complex multi-gate structures to be built through manageable sequential operations, resolving the contradiction between achieving complex gate control and maintaining fabrication simplicity
Solution Approach 2:
Mandrels are formed in advance as sacrificial structures that define the positions of subsequent spacers and gate features. This preliminary action enables precise spatial arrangement of multi-gate structures before actual gate formation, improving gate control while systematic planning reduces overall fabrication complexity
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The spacer structures self-align to the mandrels and subsequently formed gate features through conformal deposition processes. This self-alignment mechanism automatically maintains precise dimensional relationships at scaled dimensions without requiring additional alignment steps, thereby improving manufacturing precision while maintaining productivity
Solution Approach 2:
The patent employs multiple deposition thickness parameters for different spacer layers and selective etching depths to precisely control feature dimensions at scaled sizes. By adjusting these deposition and etch parameters, accurate feature size control is achieved throughout the fabrication process, resolving the contradiction between scaling down for productivity and maintaining manufacturing precision
3Reliability
If gate-all-around transistor design is implemented to enhance gate control, then device performance is improved, but fabrication difficulty increases
Solution Approach 1:
The gate structure is formed by nesting multiple layers including first spacers around mandrels, then second spacers around the first spacers, creating a nested configuration that evolves into the gate-all-around structure. This nesting approach systematically builds the complex three-dimensional gate control geometry through sequential conformal deposits, making the fabrication process more manageable despite the increased structural complexity
Solution Approach 2:
The fabrication process transitions from two-dimensional planar structures to three-dimensional gate-all-around structures through vertical stacking of spacer layers and selective removal. This dimensionality change enables comprehensive gate control around the channel from all directions while the systematic layer-by-layer construction approach keeps fabrication difficulty manageable
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure penetrates through the first dielectric layer, and a top surface of the gate structure is higher than a top surface of the S/D contact structure.