GAA Transistor Source/Drain Dislocation Control by Epitaxy
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Solution Overview
Problem
The complexity of processing and manufacturing Gate-All-Around (GAA) transistors has increased due to scaling down, necessitating improved methods for forming source/drain regions with controlled dislocations to enhance transistor performance.
Innovation Solution
The formation of GAA transistors involves adjusting processes to create dislocations in the source/drain regions by varying deposition conditions, such as growth rate and temperature, to ensure dislocations are formed without etch-back processes, allowing for controlled dislocation growth and integration into the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down is performed to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying deposition conditions (growth rate, temperature) to control dislocation formation in source/drain regions. This allows the processing method to adapt to scaled-down geometries while maintaining manufacturing feasibility, thereby resolving the contradiction between increased functional density and processing complexity
2Ease of manufacture
If conventional etch-back processes are used to form source/drain regions, then manufacturing simplicity is maintained, but dislocation control and transistor performance are insufficient
Solution Approach 1:
The patent changes the deposition parameters (growth rate, temperature) to enable controlled dislocation formation that improves transistor performance while maintaining a relatively simple manufacturing process. This resolves the contradiction by showing that parameter optimization can enhance reliability without significantly complicating the manufacturing流程
Solution Approach 2:
The patent converts the typically harmful effect of dislocations into a beneficial feature by controlling their formation through specific deposition parameters. The dislocations, which would normally degrade device performance, are instead used to enhance transistor characteristics, thereby improving reliability while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality source/drain regions with controlled dislocations, improving transistor performance and reliability.
Implementation Method 1
The structures and methods disclosed herein relate generally to semiconductors and to the formation and processing of semiconductor wafers. More particularly, the disclosed embodiments relate to gate-all-around (GAA) transistors and to the formation and processing of GAA transistor source/drain regions
Implementation Method 2
adjusting processes to create dislocations in the source/drain regions by varying deposition conditions, such as growth rate and temperature
Data Source
AI summary
A method includes forming a protruding feature. The protruding feature includes a first sacrificial nanosheet over a bulk semiconductor substrate, a first semiconductor nanosheet over the first sacrificial nanosheet, a second sacrificial nanosheet over the first semiconductor nanosheet, and a second semiconductor nanosheet over the second sacrificial nanosheet. The method further includes forming a dummy gate stack on the protruding feature, etching the protruding feature to form a recess, forming a source/drain region in the recess, wherein dislocations are formed in the source/drain region, removing the first sacrificial nanosheet and the second sacrificial nanosheet, and forming a replacement gate stack to replace the dummy gate stack.