GAA Transistor Doping Profile Tuning for Lower Channel Resistance

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing advanced ICs due to increased complexity and power dissipation issues as device geometry decreases and functional density increases.

Innovation Solution

The method involves forming a gate all around (GAA) transistor structure with epitaxial stacks of sacrificial and channel layers, followed by ion implantation of fluorine and subsequent annealing to adjust the boron junction and reduce channel resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidpower dissipation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the physical and chemical parameters of the semiconductor structure by implementing fluorine ion implantation followed by annealing treatment. This modifies the doping profile and material properties to reduce power dissipation while maintaining the scaled geometry, directly addressing the energy loss issue that arises from continued miniaturization

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ion implantation of fluorine is performed to reduce channel resistance, then drive current performance is improved, but dopant profile control becomes more challenging

Engineering Contradiction:
Improvedrive current performanceVSAvoiddopant profile control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by performing fluorine ion implantation before the final annealing step. This preliminary doping followed by thermal treatment allows the dopant profile to be established and then optimized, achieving precise control over the final doping distribution while ensuring good drive current performance

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The annealing process acts as an intermediary mechanism that mediates between the ion implantation step and the final dopant profile. The thermal treatment enables controlled diffusion and redistribution of fluorine atoms, transforming the implantation damage and concentration profile into the desired final state with precise dopant distribution

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces channel resistance and improves drive current performance by pushing the boron junction into the Si channel, while maintaining epitaxial quality and ensuring good Vt uniformity.

Implementation Method 1

implanting fluorine ions into the source/drain epitaxial structure

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the channel layers

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

diffuse the p-type doping species into a side region of a topmost one of the channel layers

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20250126859A1Semiconductor device and manufacturing method thereof
Publication Date: 2025.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250126859A1 patent drawing
  • US20250126859A1 patent drawing
  • US20250126859A1 patent drawing

AI summary

A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.