GAA Transistor Epitaxy and Oxidation for Uniform Inner Spacers
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits (ICs) due to increased complexity introduced by scaling down semiconductor IC dimensions.
Innovation Solution
The proposed solution involves a method of manufacturing semiconductor devices that includes forming a semiconductor stack with alternating first and second semiconductor layers, patterning the stack to form fin structures, and etching recesses in the fin structures to create a specific structure for gate-all-around (GAA) transistor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor IC dimensions are scaled down to improve production efficiency and lower costs, then productivity and cost are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into multiple alternating layers (first semiconductor layers and second semiconductor layers) with different compositions and properties. This segmentation allows each layer to be optimized independently for specific functions, enabling continued scaling while managing manufacturing complexity through modular layer-by-layer fabrication processes
Solution Approach 2:
The patent implements local quality by creating regions with different semiconductor compositions (e.g., SiGe vs. Si layers) in specific locations within the structure. This allows different areas to have tailored electrical and mechanical properties, enabling advanced device functionality at scaled dimensions without requiring complete process redesign
2Reliability
If alternating first and second semiconductor layers are formed to create GAA transistor structures, then device performance and reliability are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the complete alternating layer structure (first and second semiconductor layers) before subsequent processing steps. This preliminary formation of the layered structure enables later gate-all-around fabrication to proceed more reliably, as the foundation is already in place, reducing variability and improving device consistency
Solution Approach 2:
The patent implements nesting by creating gate structures that completely surround the semiconductor channels in a gate-all-around configuration. The gate structure is nested within the layered semiconductor structure, providing three-dimensional control over the channel while maintaining a manageable fabrication sequence through self-aligned processes
3Manufacturing precision
If recesses are etched in fin structures to form uniform inner spacer widths, then manufacturing precision is improved, but process difficulty increases
Solution Approach 1:
The patent applies self-service through self-aligned spacer formation where the spacers automatically position themselves relative to the etched recesses and semiconductor layers. The spacer width is determined by the spacer material deposition thickness rather than requiring precise alignment steps, enabling uniform inner spacer widths while simplifying the overall manufacturing process through self-alignment mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of GAA transistors with uniform inner spacer widths and void-free epitaxy structures, improving device performance and reliability while maintaining low power consumption.
Implementation Method 1
oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized
Data Source
AI summary
A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.