Gate-All-Around Transistor Layout for Mixed Gate Stack Thickness
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Solution Overview
Problem
Existing manufacturing methods struggle to integrate device structures with gate-all-around transistors of different thicknesses, leading to poor compatibility and reduced operating performance.
Innovation Solution
The semiconductor device includes a first and second gate-all-around transistor on a semiconductor substrate, with nanostructure layers integrally formed between the source and drain regions. The nanostructure layers in the first transistor have a thickness less than those in the second transistor, and the gate stacks also differ in thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate-all-around transistors with different gate stack thicknesses are integrated using existing manufacturing methods, then device functionality is achieved, but manufacturing compatibility is poor and operating performance is reduced
Solution Approach 1:
The semiconductor substrate is divided into a first region and a second region, where each region contains transistors with uniformly sized gate stacks. This segmentation allows different regions to have different gate stack dimensions while maintaining manufacturing compatibility within each region, thereby improving both adaptability and manufacturing precision
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different gate stack thicknesses according to specific performance requirements. The first region has gate stacks with a first thickness suitable for its functional needs, while the second region has gate stacks with a second thickness optimized for its requirements, achieving local optimization of device performance
2Manufacturing precision
If transistors with different gate stack thicknesses are manufactured separately, then each transistor type achieves optimal performance, but manufacturing complexity and cost increase
Solution Approach 1:
Multiple transistor types with different gate stack thicknesses are integrated into a single semiconductor substrate using a unified manufacturing process. The method combines the fabrication of first transistors in the first region and second transistors in the second region into one coordinated process, reducing manufacturing complexity while maintaining optimal performance for each transistor type
Solution Approach 2:
The solution transitions from a single-dimensional approach (uniform gate stack thickness throughout) to a multi-dimensional approach by introducing spatial variation in gate stack thickness across different regions of the substrate. This allows different gate stack dimensions to coexist within the same manufacturing process, achieving both performance optimization and process simplification
Data Source
AI summary
The semiconductor device includes a semiconductor substrate; and a first gate-all-around transistor and a second gate-all-around transistor formed on the semiconductor substrate and spaced apart from each other in a direction parallel to a surface of the semiconductor substrate. Each of the first gate-all-around transistor and the second gate-all-around transistor includes at least one nanostructure layer between a source region and a drain region. The nanostructure layer in the first gate-all-around transistor and the nanostructure layer in the second gate-all-around transistor are integrally formed. A thickness of each part of each nanostructure layer in the first gate-all-around transistor in a length direction of the nanostructure layer is less than a thickness of a corresponding nanostructure layer in the second gate-all-around transistor. A thickness of a gate stack in the first gate-all-around transistor is greater than a thickness of a gate stack in the second gate-all-around transistor.