GAA Transistor Gate Electrode Strain Engineering
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting the production efficiency and cost.
Innovation Solution
The solution involves forming gate all-around (GAA) transistor structures using nanostructures with tensile and compressive epitaxial structures to induce strain in channel materials, improving carrier mobility and device performance. This is achieved through specific processes like double-patterning or multi-patterning, deposition of gate dielectric layers, and formation of compressive and tensile gate electrode layers using atomic layer deposition and chemical vapor deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (e.g., self-aligned dual-patterning, self-aligned triple-patterning) where each step creates a portion of the final pattern. This segmentation allows complex nanoscale features to be formed through sequential simpler steps, managing overall process complexity while achieving high functional density
Solution Approach 2:
Sacrificial structures (mandrels, spacers, or templates) are formed in advance before the final gate electrode pattern is created. These preliminary structures guide subsequent deposition and etching steps, enabling precise feature formation at reduced sizes without requiring direct patterning of the final geometry
Solution Approach 3:
The patent employs three-dimensional device architectures (e.g., FinFET, GAA nanowire structures) that extend functionality into the vertical dimension. This allows increased functional density without proportionally increasing planar fabrication complexity, as the vertical structures can be formed using adapted versions of existing planar process steps
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Self-aligned patterning techniques are used where previously formed structures automatically serve as alignment references for subsequent steps. For example, spacers are deposited conformally on mandrels and then etched back, with the mandrel itself defining the spacer position. This self-alignment mechanism maintains manufacturing precision without requiring additional alignment steps or equipment
Solution Approach 2:
The patent utilizes changes in material properties during processing (e.g., selective etch rates, differential stress, phase transitions during deposition) to achieve precise feature dimensions. By controlling process parameters such as deposition thickness, etch selectivity, and annealing conditions, precise nanoscale features are achieved despite reduced feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances carrier mobility and improves the performance of both NMOS and PMOS transistors by inducing compressive and tensile strains in channel structures, thereby addressing the challenges of scaling down in semiconductor device fabrication.
Implementation Method 1
forming a compressive gate electrode material layer over the first work function metal layer using an atomic layer deposition process
Implementation Method 2
forming a tensile gate electrode material layer over the second work function metal layer using a chemical vapor deposition process
Implementation Method 3
forming gate all-around (GAA) transistor structures using nanostructures with tensile and compressive epitaxial structures to induce strain in channel materials
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a plurality of first nanostructures, a plurality of second nanostructures, two tensile epitaxial structures, two compressive epitaxial structures, and a dielectric layer over the substrate. The method includes forming a gate dielectric layer over the first nanostructures and the second nanostructures. The method includes forming a first work function metal layer over the gate dielectric layer over the first nanostructures. The method includes forming a second work function metal layer over the gate dielectric layer over the second nanostructures. The method includes forming a compressive gate electrode layer over the first work function metal layer using an atomic layer deposition process or a chemical vapor deposition process. The method includes forming a tensile gate electrode layer over the second work function metal layer using a physical vapor deposition process.