Dual-Channel GAA Transistor Channels with Ge Diffusion Tuning
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Solution Overview
Problem
Current methods for fabricating dual channel gate-all-around (GAA) transistors face challenges, particularly at small device pitches like 40 nanometers, due to the complexity of separate epitaxial growth and patterning of stacked semiconductor layers, leading to defects and increased processing difficulty.
Innovation Solution
A method is introduced that involves growing a stack of alternating semiconductor layers, directly patterning them to create fins, removing one type of layer to form suspended nanostructures, and converting these structures by growing thin layers and performing an anneal process to drive germanium into the channel regions, simplifying the fabrication process and enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate epitaxial growth and separate patterning of stacked semiconductor layers are used to realize GAA transistors, then n-type and p-type dual channels can be formed, but the fabrication process becomes complex and defect-prone at small device pitches
Solution Approach 1:
The patent combines separate epitaxial growth and patterning operations into a single integrated process. By forming the gate structure first and then growing semiconductor layers around it, the method eliminates multiple alignment steps and reduces process complexity while maintaining precision at small device pitches
Solution Approach 2:
The gate structure is formed in advance before the semiconductor layers are grown. This preliminary formation of the gate allows subsequent epitaxial growth to be performed around a fixed structure, simplifying the overall fabrication process and reducing defects at small pitches
2Productivity
If device size is scaled down to increase production efficiency, then productivity improves, but fabrication complexity increases
Solution Approach 1:
Instead of the conventional approach of growing layers first and then forming gates, this patent inverts the sequence by forming gates first and growing semiconductor layers around them. This inversion simplifies the fabrication process at scaled dimensions, enabling higher productivity without proportionally increasing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of dual channel GAA field effect transistors with improved carrier mobility and device performance by simplifying the fabrication process and reducing defects, while maintaining control over gate structure and channel composition.
Implementation Method 1
performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin
Data Source
AI summary
A semiconductor structure includes a fin disposed on a substrate, the fin including a channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein. The semiconductor structure further includes a gate stack engaging the channel region of the fin and gate spacers disposed between the gate stack and the source and drain regions of the fin, wherein each channel of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers, wherein a concentration of germanium in the middle section of the channel is higher than a concentration of germanium in the two end sections of the channel, and wherein the middle section of the channel further includes a core portion and an outer portion surrounding the core portion with a germanium concentration profile from the core portion to the outer portion.