GAA Transistor Structure Using Reverse-Biased Junction Leakage Blocking
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Solution Overview
Problem
Conventional methods for manufacturing gate-all-around (GAA) transistors face challenges such as reduced operation performance and integration difficulties due to parasitic channel leakage and inter-band tunneling, particularly when using highly doped layers and dielectric isolation techniques.
Innovation Solution
A GAA transistor design where a semiconductor substrate beneath the channel is recessed to form a groove filled with a doped epitaxial structure, which forms reverse-biased PN junctions with the source and drain, suppressing parasitic channel leakage without inducing inter-band tunneling, and eliminates the need for complex dielectric isolation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a highly doped layer is formed below source, drain, and channel through halo implantation to suppress parasitic channel leakage, then parasitic channel leakage is suppressed, but inter-band tunneling is induced reducing operation performance
Solution Approach 1:
The patent segments the doped structure into two distinct parts: a lightly doped extension region formed before the channel layer that suppresses parasitic leakage, and the source/drain regions that maintain proper electrical characteristics. This segmentation avoids the inter-band tunneling problem caused by uniform heavy doping while still achieving leakage suppression.
Solution Approach 2:
The patent applies different doping concentrations to different spatial locations: light doping in the extension region beneath the channel for leakage suppression, and appropriate doping in source/drain regions for electrical functionality. This local differentiation resolves the contradiction between leakage suppression and operation performance.
2Object-affected harmful factors
If conventional dielectric isolation techniques are used to suppress parasitic channel leakage, then leakage is suppressed, but manufacturing complexity increases due to complicated isolation layers
Solution Approach 1:
The patent extracts the leakage suppression function from the complex dielectric isolation system and implements it directly through the lightly doped extension region formed during the epitaxial growth process. This eliminates the need for separate dielectric isolation layers and their associated manufacturing steps.
Solution Approach 2:
The extension region serves dual purposes: it forms part of the active device structure and simultaneously provides parasitic leakage suppression. This self-service approach integrates two functions into one structure, reducing overall device complexity and manufacturing steps.
3Object-affected harmful factors
If a doped epitaxial structure is formed to suppress parasitic channel leakage, then leakage suppression is improved, but integration difficulty increases if complex isolation techniques are required
Solution Approach 1:
The patent merges the extension region formation with the channel layer epitaxial growth process, creating a continuous semiconductor structure with varying doping concentrations. This integration eliminates the need for separate isolation processing steps and simplifies the overall manufacturing workflow.
Solution Approach 2:
The extension region performs multiple functions: it serves as part of the active device structure, provides parasitic leakage suppression through reverse-biased junctions, and eliminates the need for separate dielectric isolation layers. This multi-functionality improves ease of manufacture by reducing the number of required process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses parasitic channel leakage while preventing inter-band tunneling, improving operating performance and simplifying the manufacturing process of GAA transistors, leading to enhanced integration and yield.
Implementation Method 1
the doped epitaxial structure forms reverse-biased PN junctions with the source and drain, suppressing parasitic channel leakage
Data Source
AI summary
A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.