3D GAA Transistor Stacking with Selective Isotropic Etching
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Solution Overview
Problem
The challenge in semiconductor device manufacturing lies in fabricating three-dimensional (3D) devices with transistors stacked on top of each other, which requires new process integrations and unique material selections to maintain electrical performance and drive current, especially as scaling reaches single-digit nanometer nodes, where traditional two-dimensional (2D) fabrication methods are insufficient.
Innovation Solution
A method involving a substrate with a base fin structure containing alternating layers of different channel materials and sacrificial material, exposed to an isotropic etch process to selectively etch and form gate-all-around (GAA) transistors, allowing for the formation of vertically oriented channels and enabling the stacking of transistors with different materials for improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional two-dimensional (2D) fabrication methods are used, then manufacturing simplicity is maintained, but transistor density and electrical performance deteriorate at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from traditional 2D planar transistors to three-dimensional (3D) vertically stacked transistors. Multiple transistor channels are stacked vertically on top of each other, enabling increased transistor density per unit area. The base fin structure extends vertically, and channels are formed at different heights, creating a 3D architecture that overcomes the density limitations of 2D fabrication while maintaining process feasibility through systematic material layering and selective etching.
2Reliability
If multiple different channel materials are stacked vertically, then electrical performance and drive current are improved, but manufacturing precision and material selection complexity worsen
Solution Approach 1:
The vertical stack is segmented into distinct functional layers with different materials. The base fin structure comprises alternating layers of first channel material, second channel material, and sacrificial material. Each material layer is precisely formed through separate deposition processes, allowing independent optimization of electrical properties for each channel while maintaining manufacturing control through modular layer-by-layer construction.
Solution Approach 2:
A sacrificial material layer is introduced as an intermediary between the first and second channel materials. This sacrificial layer enables selective etching processes to release and separate the channels from the base fin structure. The intermediary sacrificial material facilitates precise material removal without affecting the channel materials, thereby maintaining manufacturing precision while enabling the formation of vertically stacked transistors with different channel materials.
3Power
If vertically stacked transistor channels are formed, then drive current and control are improved, but process integration complexity and etching selectivity requirements worsen
Solution Approach 1:
The patent utilizes changes in material properties and etching parameters to achieve selective removal of sacrificial material while preserving channel materials. Different etchants and etching conditions are applied based on the specific material composition of each layer. By adjusting etching parameters such as chemistry, temperature, and time, the process achieves high selectivity for sacrificial material removal, enabling vertical channel formation without requiring excessively complex process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of 3D semiconductor devices with enhanced electrical performance by allowing for the selective etching and stacking of transistors with different channel materials, improving drive current and control in field-effect transition devices, and facilitating the integration of multiple channel materials within a complementary field-effective transistor device.
Implementation Method 1
exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material relative to the other two of the first channel material, the second channel material and the sacrificial material
Data Source
AI summary
A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.