GAA Transistor Nanostructure Patterning With Protective Spacer Layers
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Solution Overview
Problem
Fabricating gate-all-around (GAA) transistors is challenging due to inter-diffusion or intermixing at interfaces of channel layers and sacrificial layers during thermal cycles, leading to composition differences and potential damage to source/drain features.
Innovation Solution
The semiconductor device incorporates channel members with an outer spacer layer having a higher dielectric constant than the inner layer, which is etched to prevent damage to source/drain features, and a gate structure that wraps around the channel members, reducing parasitic capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If thermal cycles are applied during fabrication to form channel layers and sacrificial layers, then the layers are formed and stacked, but inter-diffusion or intermixing occurs at interfaces leading to composition differences and potential damage
Solution Approach 1:
An outer spacer layer with higher dielectric constant is introduced as an intermediary between the channel layers and sacrificial layers. This outer spacer layer acts as a barrier that prevents inter-diffusion and intermixing during thermal cycles, while also protecting the source/drain features from damage. The outer spacer layer is subsequently etched away, having served its protective function temporarily.
Solution Approach 2:
The patent employs a composite structure with inner spacer layer and outer spacer layer made of different materials having different dielectric constants. The outer spacer layer has higher dielectric constant than the inner spacer layer, creating a composite material system that provides both structural support and protective functions during fabrication thermal cycles.
2Reliability
If a gate structure is formed to wrap around channel members, then gate control is improved, but parasitic capacitance is reduced which requires precise control
Solution Approach 1:
The gate structure is segmented into multiple components including inner spacers, outer spacers, and gate electrodes that wrap around the channel members. This segmentation allows for independent optimization of each component's function, with inner spacers providing structural support and outer spacers being etched to control parasitic capacitance, achieving both good gate control and low parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes inter-diffusion, maintains structural integrity, and enhances device performance by reducing parasitic capacitance and improving gate control in GAA transistors.
Implementation Method 1
The semiconductor device incorporates channel members with an outer spacer layer having a higher dielectric constant than the inner layer
Implementation Method 2
a gate structure that wraps around the channel members, reducing parasitic capacitance and improving device performance
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes a substrate and a fin-shaped that include sacrificial layers interleaved by channel layers, forming a dummy gate stack over the fin-shaped structure, forming a gate spacer layer along sidewalls of the dummy gate stack, forming source/drain trenches in the fin-shaped structure, partially etching the sacrificial layers to form inner spacer recesses, forming inner spacer features in the inner spacer recesses, forming source/drain features in the source/drain trenches, removing the dummy gate stack, selectively etching the sacrificial layers to release the channel layers channel members, cleaning the plurality of channel members, epitaxially depositing a semiconductor layer over the channel members, annealing the semiconductor layer, and forming a gate structure to wrap around each of the channel members.