GAA Transistor Channel Thickness Variation for Threshold Voltage Control
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Solution Overview
Problem
Gate-all-around (GAA) transistor structures face challenges in reducing threshold voltage variability due to uniform channel layer thicknesses, which affects device performance in downscaling efforts.
Innovation Solution
A semiconductor device design featuring a stack of vertically aligned semiconductor channel layers with alternating thicknesses, where the uppermost channel layer has a different thickness than the remaining layers, and a method of forming this structure by alternating sacrificial and channel layers, followed by etching and gate stack formation, to reduce threshold voltage variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If uniform channel layer thickness is used in GAA transistor structures, then manufacturing simplicity is maintained, but threshold voltage variability increases
Solution Approach 1:
The patent applies local quality by making the uppermost channel layer have a different thickness (first thickness) compared to the remaining channel layers (second thickness). This localized variation in the uppermost layer specifically addresses threshold voltage variability without requiring complex variations throughout the entire structure, thus resolving the contradiction between manufacturing precision and device complexity.
2Manufacturing precision
If the uppermost channel layer thickness is optimized based on work function metal, then threshold voltage control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements parameter changes by optimizing the thickness of the uppermost channel layer based on specific parameters including work function metal thickness and type. This targeted parameter optimization improves threshold voltage control while maintaining relatively simple manufacturing processes, as only the uppermost layer requires specialized thickness control rather than the entire channel stack.
Data Source
AI summary
A semiconductor device and method of forming the same including a plurality of vertically aligned semiconductor channel layers disposed above a substrate layer, a gate stack formed on, and around the vertically aligned semiconductor channel layers and source and drain elements disposed in contact with sidewalls of the vertically aligned semiconductor channel layers. An uppermost vertically aligned semiconductor channel layer has a first thickness of semiconductor material and the remaining vertically aligned semiconductor channel layers have a second thickness of semiconductor material different from the first thickness.