GAA Transistor Multilayer Work Function Structure
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Solution Overview
Problem
The scaling down of n-type and p-type field effect transistors in CMOS technology poses challenges in maintaining device performance and efficiency due to the need for smaller and more complex circuits, requiring innovative methods for forming semiconductor devices that enhance carrier mobility and reduce parasitic capacitance.
Innovation Solution
The method involves forming gate-all-around (GAA) transistor structures using an epitaxial stack with alternating layers of SiGe and Si, where the second epitaxial layers form nanowires for channel regions, and employing a multilayer work function structure with different high-k dielectric sheaths for n-type and p-type transistors to adjust work functions and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down to increase circuit density, then productivity and integration are improved, but device performance and carrier mobility deteriorate
Solution Approach 1:
The patent changes the physical and chemical parameters of the transistor structure by introducing a multi-layer channel structure with different materials (e.g., SiGe/Si alternating layers) and adjusting doping concentrations. This allows maintaining carrier mobility and device performance while scaling down transistor dimensions to increase circuit density.
Solution Approach 2:
The patent employs composite material structures in the channel region, such as alternating layers of SiGe and Si, or combinations of different semiconductor materials. These composite structures provide strain engineering benefits that enhance carrier mobility, enabling small transistors to maintain high performance and resolve the contradiction between scaling and performance retention.
2Productivity
If transistor size is scaled down, then circuit integration is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating non-uniform doping profiles and varying material compositions in different regions of the transistor. For example, higher doping concentrations are applied in specific regions to control electric fields and reduce parasitic capacitance effects, while maintaining overall small transistor dimensions for high integration.
Solution Approach 2:
The patent modifies structural parameters such as channel length, width, and thickness, as well as material parameters like dielectric constants and doping levels. These parameter changes enable optimization of the transistor to minimize parasitic capacitance while maintaining scaled-down dimensions for high circuit integration.
3Reliability
If complex multilayer work function structures are used to adjust work functions, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent designs the gate electrode structure to serve multiple functions simultaneously: it provides the primary gating function, acts as a work function adjustment layer, and serves as an interface for subsequent processing steps. This multi-functionality reduces the need for separate dedicated work function adjustment layers, thereby simplifying manufacturing while maintaining device performance.
Solution Approach 2:
The patent adjusts the work function by changing the material composition and thickness of the gate electrode layers rather than adding complex multilayer structures. For example, using different metal alloys or adjusting the thickness of existing layers provides work function tuning with simpler manufacturing processes, reducing device complexity while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved carrier mobility and device performance by straining channel regions and reducing parasitic capacitance, allowing for the formation of efficient and scalable semiconductor devices with a single metal layer gate electrode, simplifying deposition processes and enhancing device design.
Implementation Method 1
forming a first plurality of epitaxial layers and a second plurality of epitaxial layers alternately on a substrate
Implementation Method 2
improved carrier mobility and device performance by straining channel regions
Data Source
AI summary
A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.